公开(公告)号：WO2003027847A1

公开(公告)日：2003-04-03

申请号：PCT/US2002/028931

申请日：2002-09-11

Applicant: MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE

Inventor： STENGEL, Robert, E. ,  CAFARO, Nicholas, G.

IPC: G06F01/02

CPC classification number: G06F1/025

Abstract: A frequency signal generator (300) generates a desired output signal Fout (365) based on the ratio of the frequency a reference clock signal (301) to that of the desired output signal (Fclk / Fout) = N +R, where the N is an integer portion and R is a fractional portion of the ratio. A counter (320) generates a counter overflow signal based on counting a minimum of N transitions of the reference clock signal. An accumulator (330) accumulates the fractional portion R in response to the counter overflow signal (325), and outputs the accumulated value (335) that is preferably used as address information for selecting one of a number of delay paths (340, 350) for outputting the desired output signal.

Abstract translation: 频率信号发生器（300）基于频率参考时钟信号（301）与期望输出信号（Fclk / Fout）= N + R的频率的比率产生期望的输出信号Fout（365），其中N 是整数部分，R是该比率的小数部分。 计数器（320）基于对参考时钟信号的N个转换的最小值进行计数来生成计数器溢出信号。 累加器（330）响应于计数器溢出信号（325）积累分数部分R，并且输出优选地用作用于选择多个延迟路径（340,350）中的一个的地址信息的累加值（335） 用于输出所需的输出信号。

公开(公告)号：WO2003017373A2

公开(公告)日：2003-02-27

申请号：PCT/US2002/025342

申请日：2002-08-09

Applicant: MOTOROLA, INC. A CORPORATION OF THE STATE OF DELAWARE

Inventor： HIGGINS, JR., Robert, J. ,  STENGEL, Robert, E.

IPC: H01L27/20

CPC classification number: H01L21/02521 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02488 ,  H01L21/02505 ,  H01L27/20 ,  H01L41/0815 ,  H01L41/1873 ,  H01L41/319 ,  H03H9/02566 ,  H03H9/02574

Abstract: High quality layers of monocrystalline materials (26) can be grown overlying monocrystalline substrates (22, 2615) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24,2610) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating bufferlayer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. The use of monocrystalline piezoelectric material as an overlying layer (2605) is disclosed to facilitate the fabrication of on-chip high frequency communications devices such as microwave SAW devices with direct interface to high speed semiconductor devices in the integrated circuit.

Abstract translation: 通过形成用于生长单晶层的柔性衬底，可以在单晶衬底（22,2615）（例如大硅晶片）上生长高质量的单晶材料层（26）。 适应缓冲层（24,2610）包括由硅氧化物的非晶界面层与硅晶片隔开的单晶氧化物层。 无定形界面层（28）消除应变并允许高质量单晶氧化物容纳缓冲层的生长。 适应缓冲层与下面的硅晶片和上面的单晶材料层晶格匹配。 适应缓冲层和下面的硅衬底之间的任何晶格失配都由无定形界面层来处理。 另外，柔性衬底的形成可以包括利用表面活性剂增强外延，单晶硅在单晶氧化物上的外延生长以及Zintl相材料的外延生长。 公开了使用单晶压电材料作为上覆层（2605），以便于制造片上高频通信器件，例如与集成电路中的高速半导体器件直接接口的微波SAW器件。

公开(公告)号：WO2003012861A1

公开(公告)日：2003-02-13

申请号：PCT/US2002/014463

申请日：2002-05-08

Applicant: MOTOROLA, INC. A CORPORATION OF THE STATE OF DELAWARE

Inventor： STENGEL, Robert, E. ,  HIGGINS, Jr., Robert, J.

IPC: H01L21/8258

CPC classification number: H01L27/0605 ,  H01L21/8258 ,  H01L27/0688

Abstract: A semiconductor apparatus for effecting a plurality of functions involving high frequency signals and low frequency signals includes: (a) at least one first circuit section implemented in at least one first semiconductor material; and (b) at least one second circuit section implemented in at least one second semiconductor material. The at least one second semiconductor material exhibits lower noise generating characteristics than the at least one first semiconductor material at the low frequency signals. The at least one first circuit section and the at least one second circuit section are implemented in an integrated circuit construction. Preferably the integrated circuit construction is a monolithic configuration. Preferably the at least one first semiconductor material includes gallium arsenide. Preferably the at least one second semiconductor material includes silicon.

Abstract translation: 用于实现涉及高频信号和低频信号的多个功能的半导体装置包括：（a）至少一个第一电路部分，其实现在至少一个第一半导体材料中; 和（b）在至少一个第二半导体材料中实现的至少一个第二电路部分。 所述至少一个第二半导体材料在所述低频信号下表现出比所述至少一个第一半导体材料更低的噪声产生特性。 所述至少一个第一电路部分和所述至少一个第二电路部分以集成电路结构实现。 优选地，集成电路结构是单片结构。 优选地，至少一个第一半导体材料包括砷化镓。 优选地，至少一个第二半导体材料包括硅。

公开(公告)号：WO1996030959A1

公开(公告)日：1996-10-03

申请号：PCT/US1996003673

申请日：1996-03-21

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  BAI, Lijun ,  LIAN, Ke, Keryn ,  STENGEL, Robert, E.

IPC: H01M10/44

CPC classification number: H01M4/38 ,  H01M10/44 ,  H01M2300/0014

Abstract: An electrochemical charge storage device (20) having a voltage discharge profile which is constant for a substantial period of the discharge cycle, which then drops off sharply to full discharge, in a manner more often associated with a battery discharge profile. The electrochemical charge storage device is further characterized by a discharge rate in excess of at least 100 C, and as much as 7000 C. Accordingly, the electrochemical charge storage device is characterized by a battery discharge voltage profile which occurs at substantially capacitor discharge rates.

Abstract translation: 电化学电荷存储装置（20）具有电压放电曲线，该电压放电曲线在放电周期的相当长的时间段内是恒定的，然后以更经常地与电池放电曲线相关联的方式急剧下降至全放电。 电化学电荷存储装置的特征还在于放电速率超过至少100℃，高达7000℃。因此，电化学电荷存储装置的特征在于以基本上电容器放电速率发生的电池放电电压分布。

公开(公告)号：WO1994011799A1

公开(公告)日：1994-05-26

申请号：PCT/US1993010872

申请日：1993-11-10

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  STENGEL, Robert, E.

IPC: G05F01/613

CPC classification number: H03F3/2173 ,  H02M3/158 ,  H02M7/483 ,  H03F1/0227 ,  H03F2200/351

Abstract: A voltage regulator (200) includes a controller (204) which selectively activates a plurality of switching means (208, 210, 214 and 212) in order to select between a first current loop in which an energy storage device is charged by an input supply and a second loop in which the energy storage device is coupled to the output terminal (242) of the regulator (200). The switching from the second current loop to the first is governed by the controller (204) determining that the loop current in the second loop has reached a predetermined level. A first switching audio amplifier (300) is disclosed which uses the voltage regulator (200) to provide a continuously variable output voltage (318) in order to provide for high quality amplification which is independent of the volume setting. A second audio amplifier (400) includes a converter (436) which provides discrete voltage levels to a full wave bridge in order to provide improved audio output.

Abstract translation: 电压调节器（200）包括控制器（204），其选择性地激活多个开关装置（208,210,214和212），以便在第一电流回路中选择能量存储装置由输入电源 以及其中所述能量存储装置耦合到所述调节器（200）的输出端子（242）的第二回路。 从第二电流回路切换到第一电流回路由控制器（204）决定第二回路中的回路电流已经达到预定水平。 公开了一种第一开关音频放大器（300），其使用电压调节器（200）来提供连续可变的输出电压（318），以便提供与音量设置无关的高质量放大。 第二音频放大器（400）包括向全波桥提供离散电压电平的转换器（436），以便提供改进的音频输出。

公开(公告)号：WO1992008295A1

公开(公告)日：1992-05-14

申请号：PCT/US1991007456

申请日：1991-10-10

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  STENGEL, Robert, E.

IPC: H04B01/16

CPC classification number: H04W52/0229 ,  Y02D70/00

Abstract: A receiver 100 used for recovering modulation signals modulated on a carrier signal is disclosed. The receiver 100 includes a detector 204 and a decoder 206 for detecting the presence of a non-valid coded squelch signal and decoding such signal in the recovered modulation signal. The receiver 100 further includes a synchronizer 208 for synchronizing the detected non-valid coded signal. Receiver 100 is placed in a battery saver mode when a non-valid coded squelch signal is detected. The battery saver mode includes monitoring the recovered modulation signal for a change in the non-valid coded squelch signal. The battery saver mode is departed once a change in the non-valid coded squelch signal is detected.

公开(公告)号：EP1716639A2

公开(公告)日：2006-11-02

申请号：EP05706041.0

申请日：2005-01-25

Applicant: MOTOROLA, INC.

Inventor： TOMERLIN, Andrew, T. ,  STENGEL, Robert, E.

IPC: H03H11/26

CPC classification number: H03L7/0802 ,  H03K5/133 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/16

Abstract: A configurable circuit consistent with certain embodiments has a variable length delay line (10), the delay line (10) having an input (24) and having N delay elements (12, 14, 16, 18,…, 20) to provide a plurality of N delayed outputs (T(0) through T(N)). The variable length delay line (10) also has a number of active delay elements determined by a program command. A configurable processing array (32) receives the delayed outputs from the active delay elements and secondary data (38). The configurable processing array has an array of configurable circuit elements (104, 130, 150). The configurable processing array is configured to process the delayed outputs and the secondary data (38) in a manner for which the invention is to be used. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

公开(公告)号：EP0979551A1

公开(公告)日：2000-02-16

申请号：EP98920127.2

申请日：1998-04-30

Applicant: MOTOROLA, INC.

Inventor： STENGEL, Robert, E. ,  OLSON, Scott, A.

IPC: H03F3/68

CPC classification number: H03F3/602 ,  H03F1/0294

Abstract: An apparatus (100) uses power recovery from a combining circuit (125) to improve efficiency. A power combiner (125) generates multiple output signals (127, 133) from a combination of input signals (113, 114). One of the output signals from the power combiner is coupled to a power recovery circuit (135), and energy is recovered and preferably stored for later use.

公开(公告)号：EP0818057A1

公开(公告)日：1998-01-14

申请号：EP96910466.0

申请日：1996-03-21

Applicant: MOTOROLA, INC.

Inventor： BAI, Lijun ,  LIAN, Ke, Keryn ,  STENGEL, Robert, E.

IPC: H01G9 ,  H01M4 ,  H01M10

CPC classification number: H01M4/38 ,  H01M10/44 ,  H01M2300/0014

Abstract: An electrochemical charge storage device (20) having a voltage discharge profile which is constant for a substantial period of the discharge cycle, which then drops off sharply to full discharge, in a manner more often associated with a battery discharge profile. The electrochemical charge storage device is further characterized by a discharge rate in excess of at least 100 C, and as much as 7000 C. Accordingly, the electrochemical charge storage device is characterized by a battery discharge voltage profile which occurs at substantially capacitor discharge rates.

公开(公告)号：EP0554386B1

公开(公告)日：1997-07-16

申请号：EP91920601.1

申请日：1991-10-10

Applicant: MOTOROLA INC.

Inventor： STENGEL, Robert, E.

IPC: H04B1/16

CPC classification number: H04W52/0229 ,  Y02D70/00

Abstract: A receiver 100 used for recovering modulation signals modulated on a carrier signal is disclosed. The receiver 100 includes a detector 204 and a decoder 206 for detecting the presence of a non-valid coded squelch signal and decoding such signal in the recovered modulation signal. The receiver 100 further includes a synchronizer 208 for synchronizing the detected non-valid coded signal. Receiver 100 is placed in a battery saver mode when a non-valid coded squelch signal is detected. The battery saver mode includes monitoring the recovered modulation signal for a change in the non-valid coded squelch signal. The battery saver mode is departed once a change in the non-valid coded squelch signal is detected.