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公开(公告)号：US11449271B2
公开(公告)日：2022-09-20
申请号：US17079048
申请日：2020-10-23
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Mark A. Helm , Giuseppina Puzzilli , Peter Feeley , Yifen Liu , Violante Moschiano , Akira Goda , Sampath K. Ratnam
IPC: G06F3/06
Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.
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公开(公告)号：US20220199163A1
公开(公告)日：2022-06-23
申请号：US17127358
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Scott A. Stoller , Pitamber Shukla , Priya Venkataraman , Giuseppina Puzzilli , Niccolo' Righetti
Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.
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公开(公告)号：US11360700B2
公开(公告)日：2022-06-14
申请号：US16995645
申请日：2020-08-17
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.
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公开(公告)号：US20220068407A1
公开(公告)日：2022-03-03
申请号：US17001757
申请日：2020-08-25
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, JR. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo' Righetti
Abstract: A change in a read window of a group of memory cells of a memory device that has undergone a plurality of program/erase cycles (PECs) can be determined. read voltage can be determined based at least in part on the determined change in the read window.
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公开(公告)号：US09490025B2
公开(公告)日：2016-11-08
申请号：US14143763
申请日：2013-12-30
Applicant: Micron Technology, Inc.
Inventor： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C2211/5621
Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
Abstract translation: 编程存储器件的方法包括将多条数据线的每条数据线偏置到编程禁止电压; 放电多条数据线的数据线的第一部分，其中多条数据线的数据线的第一部分耦合到选择用于编程的存储器单元; 以及将多个编程脉冲施加到被选择用于编程的存储器单元，同时将所述多条数据线的数据线的剩余部分偏置到所述编程禁止电压。
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Patent Agency Ranking
公开(公告)号：US20150029788A9
公开(公告)日：2015-01-29
申请号：US14143763
申请日：2013-12-30
Applicant: Micron Technology, Inc.
Inventor： Akira Goda , Andrew Bicksler , Violante Moschiano , Giuseppina Puzzilli
IPC: G11C16/34
CPC classification number: G11C16/3427 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/3418 , G11C2211/5621
Abstract: Methods of programming memory devices include biasing each data line of a plurality of data lines to a program inhibit voltage; discharging a first portion of data lines of the plurality of data lines, wherein the first portion of data lines of the plurality of data lines are coupled to memory cells selected for programming; and applying a plurality of programming pulses to the memory cells selected for programming while biasing a remaining portion of data lines of the plurality of data lines to the program inhibit voltage.
Abstract translation: 编程存储器件的方法包括将多条数据线的每条数据线偏置到编程禁止电压; 放电多条数据线的数据线的第一部分，其中多条数据线的数据线的第一部分耦合到选择用于编程的存储器单元; 以及将多个编程脉冲施加到被选择用于编程的存储器单元，同时将所述多条数据线的数据线的剩余部分偏置到所述编程禁止电压。
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公开(公告)号：US11941285B2
公开(公告)日：2024-03-26
申请号：US17235216
申请日：2021-04-20
Applicant: Micron Technology, Inc.
Inventor： Vamsi Pavan Rayaprolu , Kishore Kumar Muchherla , Ashutosh Malshe , Giuseppina Puzzilli , Saeed Sharifi Tehrani
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, receiving a read request to perform a read operation on a block of the memory device; determining whether an entry corresponding to the block is stored in a data structure associated with the memory device; responsive to the entry being stored in the data structure, incrementing a counter associated with the block to track a number of read operations performed on the block of the memory device; resetting a timer associated with the block to an initial value, wherein the timer is to track a period of time that elapses since the read operation was performed on the block of the memory device; determining that the counter and the timer satisfy a first criterion; and responsive to determining that the counter and the timer satisfy the first criterion, removing the entry corresponding to the block from the data structure associated with the memory device.
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公开(公告)号：US11789629B2
公开(公告)日：2023-10-17
申请号：US17846462
申请日：2022-06-22
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo' Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
IPC: G06F3/06
CPC classification number: G06F3/0644 , G06F3/0616 , G06F3/0619 , G06F3/0653 , G06F3/0656 , G06F3/0673
Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.
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公开(公告)号：US11775208B2
公开(公告)日：2023-10-03
申请号：US17829861
申请日：2022-06-01
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Niccolo′ Righetti , Jeffrey S. McNeil, Jr. , Akira Goda , Todd A. Marquart , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
CPC classification number: G06F3/0656 , G06F1/263 , G06F3/0613 , G06F3/0619 , G06F3/0644 , G06F3/0653 , G06F3/0673
Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.
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公开(公告)号：US11762767B2
公开(公告)日：2023-09-19
申请号：US17302064
申请日：2021-04-22
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Giuseppina Puzzilli , Vamsi Pavan Rayaprolu , Ashutosh Malshe , James Fitzpatrick , Shyam Sunder Raghunathan , Violante Moschiano , Tecla Ghilardi
CPC classification number: G06F12/0269 , G11C16/3418 , G11C29/52 , G06F2212/702 , G11C16/0483
Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.
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