公开(公告)号：US11783901B2

公开(公告)日：2023-10-10

申请号：US17880980

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/04

CPC classification number: G11C16/34 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0727 ,  G06F11/0793 ,  G11C16/26 ,  G11C16/0483

Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

公开(公告)号：US11782847B2

公开(公告)日：2023-10-10

申请号：US17898138

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Ashutosh Malshe

IPC: G06F12/123 ,  G06F12/02 ,  G06F11/30

CPC classification number: G06F12/123 ,  G06F11/3037 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/70 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: A first block that is assigned a first sequence identifier can be identified. A determination can be made as to whether the assigned first sequence identifier satisfies a threshold sequence identifier condition that corresponds to a difference between the first sequence identifier assigned to the first block and second sequence identifier assigned to a second block. In response to determining that the assigned first sequence identifier satisfies the threshold sequence identifier condition, a media management operation can be performed on the first block.

公开(公告)号：US11775181B2

公开(公告)日：2023-10-03

申请号：US17708735

申请日：2022-03-30

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Harish Reddy Singidi ,  Ting Luo ,  Kishore Kumar Muchherla

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

公开(公告)号：US20230289062A1

公开(公告)日：2023-09-14

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US11748013B2

公开(公告)日：2023-09-05

申请号：US17949977

申请日：2022-09-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Peter Feeley ,  Karl D. Schuh

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04

CPC classification number: G06F3/064 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G11C16/10 ,  G11C16/0483

Abstract: An initial value of a power cycle count associated with the memory device is identified. The power cycle count is incremented responsive to detecting a powering up of the memory device. Responsive to programming a block residing in the memory device, the block is associated with a current block family associated with the memory device. A currently value of the power cycle count is determined. Responsive to determining that a difference between the initial value of the power cycle count and the current value of the power cycle count satisfies a predefined condition, the current block family is closed.

公开(公告)号：US11726874B2

公开(公告)日：2023-08-15

申请号：US17249399

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Vamsi Rayaprolu ,  Sivagnanam Parthasarathy ,  Sampath K. Ratnam ,  Peter Feeley ,  Kishore Kumar Muchherla

IPC: G06F11/10 ,  G06F11/00 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1012

Abstract: A request to retrieve user data stored at a memory device is received and a first error control operation associated with the user data is performed. An indication of a failure of the first error control operation is received, and in response, a subset of system data stored at the memory device is identified. A second error control operation is performed on the subset of the system data to retrieve the subset of the system data stored at the memory device, and the user data is read by using the subset of the system data retrieved based on the performing of the second error control operation.

公开(公告)号：US11699491B2

公开(公告)日：2023-07-11

申请号：US17247643

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C16/20 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C2211/561

Abstract: Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.

公开(公告)号：US11676664B2

公开(公告)日：2023-06-13

申请号：US17883538

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Peter Feeley ,  Jiangang Wu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3495

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.

公开(公告)号：US20230176741A1

公开(公告)日：2023-06-08

申请号：US17979534

申请日：2022-11-02

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil ,  Eric N. Lee ,  Vamsi Pavan Rayaprolu ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Patrick R. Khayat ,  Violante Moschiano

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0679 ,  G06F3/0653

Abstract: Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.

公开(公告)号：US11670381B2

公开(公告)日：2023-06-06

申请号：US17313249

申请日：2021-05-06

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C29/02 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C16/08 ,  G11C16/24 ,  G11C2207/2254

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.