公开(公告)号：US20250021269A1

公开(公告)日：2025-01-16

申请号：US18770982

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Sampath Ratnam

IPC: G06F3/06

Abstract: Various embodiments provide for performing a preconditioned operation on a memory system (e.g., the memory sub-system) based on queue identifiers of command requests received from a host system, where the precondition can include detection of command requests to be performed (e.g., executed) with respect to a sequence of memory addresses.

公开(公告)号：US20250021267A1

公开(公告)日：2025-01-16

申请号：US18770926

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Luca Bert ,  Sampath Ratnam

IPC: G06F3/06

Abstract: Various embodiments provide for block caching with queue identifiers on a memory system. In particular, when a write request to write host data is executed on a memory system that uses write/block caching and the host data is written to one or more cache blocks of a memory device of the memory system, the memory system can cause the queue identifier of the write request to be stored on the memory system in association with the host data. Subsequently, when the memory system moves (e.g., de-stages) data from one or more cache blocks (e.g., single-level cell (SLC) blocks) to one or more non-cache blocks (e.g., quad-level cell (QLC) blocks), the memory system can do so based on queue identifiers associated with host data written on one or more cache blocks of the memory system.

公开(公告)号：US11887651B2

公开(公告)日：2024-01-30

申请号：US17745262

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC: G11C11/406 ,  G06F13/16 ,  G11C7/04

CPC classification number: G11C11/40626 ,  G06F13/1636 ,  G11C7/04 ,  G11C11/40615 ,  G11C2211/4061

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US11670381B2

公开(公告)日：2023-06-06

申请号：US17313249

申请日：2021-05-06

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi ,  Peter Sean Feeley ,  Sampath Ratnam ,  Kulachet Tanpairoj ,  Ting Luo

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/28 ,  G11C16/34 ,  G11C29/02 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/28 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C16/08 ,  G11C16/24 ,  G11C2207/2254

Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

公开(公告)号：US20220171713A1

公开(公告)日：2022-06-02

申请号：US17399997

申请日：2021-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ashutosh Malshe ,  Sampath Ratnam ,  Kishore Kumar Muchherla ,  Peter Feeley

IPC: G06F12/10 ,  G06F12/02

Abstract: At least one source physical memory block stored in a memory device is identified. The source physical memory block comprises at least one logical unit. A determination is made as to whether an age characteristic of the logical unit satisfies a threshold criterion. A storage classification is determined for the logical unit based on whether the age characteristic of the logical unit satisfies the threshold criterion. The classification comprises a hot data classification or a cold data classification. A target physical memory block is identified based on the storage classification determined for the logical unit, and the logical unit is stored in the identified target physical memory block.

公开(公告)号：US11335394B2

公开(公告)日：2022-05-17

申请号：US17238846

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC: G11C7/00 ,  G11C11/406 ,  G06F13/16 ,  G11C7/04

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US11068197B2

公开(公告)日：2021-07-20

申请号：US16460401

申请日：2019-07-02

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Sean Feeley ,  Ashutosh Malshe ,  Sampath Ratnam ,  Harish Reddy Singidi ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US11037630B2

公开(公告)日：2021-06-15

申请号：US16856955

申请日：2020-04-23

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath Ratnam ,  Preston Allen Thomson ,  Harish Reddy Singidi ,  Jung Sheng Hoei ,  Peter Sean Feeley ,  Jianmin Huang

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/22 ,  G11C16/04 ,  G11C16/34 ,  G11C16/28 ,  G11C29/02 ,  G11C16/20 ,  G11C11/56

Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.

公开(公告)号：US11023177B2

公开(公告)日：2021-06-01

申请号：US16909503

申请日：2020-06-23

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Karl D. Schuh ,  Ashutosh Malshe ,  Kishore Kumar Muchherla ,  Vamsi Pavan Rayaprolu ,  Sampath Ratnam ,  Harish Reddy Singidi ,  Renato Padilla, Jr.

IPC: G11C16/04 ,  G06F3/06 ,  G06F12/1009 ,  G11C16/34 ,  G11C16/26

Abstract: A memory device may receive a read request describing a logical address at the memory device. The memory device may obtain a table entry associated with the logical address. The table entry comprises a physical address corresponding to the logical address and a write temperature data indicating a write temperature for the logical address. The memory device may determine a corrected threshold voltage for reading the physical address based at least in part on the write temperature data and read the physical address using the corrected threshold voltage.

公开(公告)号：US20200251162A1

公开(公告)日：2020-08-06

申请号：US16855579

申请日：2020-04-22

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, JR.

IPC: G11C11/406 ,  G06F13/16

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.