公开(公告)号：WO2016028637A1

公开(公告)日：2016-02-25

申请号：PCT/US2015/045288

申请日：2015-08-14

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Young Kyu ,  WE, Hong Bok ,  KIM, Dong Wook ,  HWANG, Kyu-Pyung

IPC: H01L23/373 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H05K1/0207 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer.

Abstract translation: 本文提供了一种集成器件，其包括衬底，管芯，位于衬底和管芯之间的散热层和被配置为将管芯耦合到散热层的第一互连。 散热层可以被配置成为接地信号提供电路径。 第一互连可以被进一步配置成将热量从管芯传导到散热层。 集成器件还可以包括配置成将管芯耦合到衬底的第二互连。 第二互连可以被进一步配置为在管芯和衬底之间传导功率信号。 集成器件还可以包括位于散热层和衬底之间的介电层，以及位于管芯和散热层之间的阻焊层。

公开(公告)号：WO2015160671A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/025435

申请日：2015-04-10

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Chin-Kwan ,  KIM, Dong Wook ,  LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/48

CPC classification number: H01L21/768 ,  H01L21/4857 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/49822 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014

Abstract: An integrated circuit (IC) substrate that includes a second patterned metal layer formed in between a first patterned metal layer is disclosed. A dielectric layer formed on the first patterned metal layer separates the two metal layers. A non-conductive layer is formed on the dielectric layer and the second patterned metal layer.

Abstract translation: 公开了一种集成电路（IC）基板，其包括形成在第一图案化金属层之间的第二图案化金属层。 形成在第一图案化金属层上的电介质层分离两个金属层。 在介电层和第二图案化金属层上形成非导电层。

公开(公告)号：WO2015126639A1

公开(公告)日：2015-08-27

申请号：PCT/US2015/014885

申请日：2015-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC: H01L23/498 ,  H01L23/50

CPC classification number: H03K3/013 ,  G05F3/08 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/13091 ,  H01L2924/15311 ,  H05K1/0306 ,  H05K1/183 ,  H05K1/184 ,  H05K3/306 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/49139 ,  H01L2924/00

Abstract: An embedded multi-terminal capacitor embedded in a substrate cavity includes at least one metal layer patterned into a plurality of power rails and a plurality of ground rails. The substrate includes an external power network.

Abstract translation: 嵌入在衬底空腔中的嵌入式多端子电容器包括图案化成多个电源轨道和多个接地轨道的至少一个金属层。 基板包括外部电力网络。

公开(公告)号：WO2015048368A1

公开(公告)日：2015-04-02

申请号：PCT/US2014/057584

申请日：2014-09-26

Applicant: QUALCOMM INCORPORATED

Inventor： KIM, Dong Wook ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  YUN, Changhan Hobie

IPC: H01L23/16 ,  H01L23/00

CPC classification number: H01L21/52 ,  H01L21/4817 ,  H01L23/04 ,  H01L23/13 ,  H01L23/16 ,  H01L28/60 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Systems and methods for preventing warpage of a semiconductor substrate in a semiconductor package (200). A continuous or uninterrupted stiffener structure (208) is designed with a recessed groove (208b), such that passive components, such as, high density capacitors are housed within the recessed groove. The stiffener structure with the recessed groove is attached to the semiconductor substrate (202) using anisotropic conductive film (ACF) or anisotropic conductive paste (ACP). The stiffener structure with the recessed groove surrounds one or more semiconductor devices (204) that may be formed on the semiconductor substrate. The stiffener structure with the recessed groove does not extend beyond horizontal boundaries of the semiconductor substrate.

Abstract translation: 用于防止半导体封装（200）中的半导体衬底翘曲的系统和方法。 连续或不间断的加强结构（208）设计有凹槽（208b），使得诸如高密度电容器的无源部件容纳在凹槽内。 具有凹槽的加强结构使用各向异性导电膜（ACF）或各向异性导电膏（ACP）附着在半导体衬底（202）上。 具有凹槽的加强结构围绕可以形成在半导体衬底上的一个或多个半导体器件（204）。 具有凹槽的加强结构不延伸超过半导体衬底的水平边界。

公开(公告)号：WO2014164186A1

公开(公告)日：2014-10-09

申请号：PCT/US2014/021078

申请日：2014-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： HWANG, Kyu-Pyung ,  SONG, Young Kyu ,  KIM, Dong Wook ,  YUN, Changhan

IPC: H01L23/552 ,  H01L25/065 ,  H05K9/00 ,  H01L23/66

CPC classification number: H01L23/552 ,  H01L21/82 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16245 ,  H01L2224/17515 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K9/0007 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One feature pertains to a multi-chip package that includes a substrate and an electromagnetic interference (EMI) shield coupled to the substrate. At least one integrated circuit is coupled to a first surface of the substrate. The EMI shield includes a metal casing configured to shield the package from radio frequency radiation, a dielectric layer coupled to at least a portion of an inner surface of the metal casing, and a plurality of signal lines. The signal lines are coupled to the dielectric layer and electrically isolated from the metal casing by the dielectric layer. At least one other integrated circuit is coupled to an inner surface of the EMI shield, and at least a portion of the inner surface of the EMI shield faces the first surface of the substrate. The signal lines are configured to provide electrical signals to the second circuit component.

Abstract translation: 一个特征涉及包括衬底和耦合到衬底的电磁干扰（EMI）屏蔽）的多芯片封装。 至少一个集成电路耦合到衬底的第一表面。 EMI屏蔽包括被配置为将封装与射频辐射屏蔽的金属外壳，耦合到金属外壳的内表面的至少一部分的电介质层和多个信号线。 信号线耦合到电介质层，并通过电介质层与金属外壳电隔离。 至少一个其它集成电路耦合到EMI屏蔽的内表面，并且EMI屏蔽的内表面的至少一部分面向基板的第一表面。 信号线被配置为向第二电路部件提供电信号。

公开(公告)号：WO2016200604A1

公开(公告)日：2016-12-15

申请号：PCT/US2016/033948

申请日：2016-05-24

Applicant: QUALCOMM INCORPORATED

Inventor： LEE, Jae Sik ,  HWANG, Kyu-Pyung ,  WE, Hong Bok

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/14 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L21/486 ,  H01L21/565 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/50 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/92225 ,  H01L2225/06548 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A package-on-package (PoP) structure includes a first die, a second die, and a memory device electrically coupled to the first die and the second die by an interposer between the first die and the second die. The interposer includes copper-filled vias formed within a mold.

Abstract translation: 封装封装（PoP）结构包括通过第一管芯和第二管芯之间的插入件电耦合到第一管芯和第二管芯的第一管芯，第二管芯和存储器件。 插入器包括在模具内形成的填充铜的通孔。

公开(公告)号：WO2016100304A1

公开(公告)日：2016-06-23

申请号：PCT/US2015/065757

申请日：2015-12-15

Applicant: QUALCOMM INCORPORATED

Inventor： WE, Hong Bok ,  KIM, Dong Wook ,  HWANG, Kyu-Pyung ,  SONG, Young Kyu

IPC: H01L23/13 ,  H01L23/14 ,  H01L23/538 ,  H01L25/10 ,  H01L21/60 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/13 ,  H01L23/142 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24247 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15311 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/3511

Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity.

Abstract translation: 本公开提供了用于制造PoP半导体封装的半导体封装和方法。 PoP半导体封装可以包括第一半导体封装，第一半导体封装包括阳极化金属盖结构，其包括（i）具有中心腔打开方向的中心空腔和（ii）至少一个周边空腔，其具有面向 在与中心腔打开方向相反的方向上，布置在阳极化金属盖结构的中心腔中的第一半导体器件，电耦合到第一半导体器件的再分配层，其中形成在再分配层中的导电迹线暴露于 所述至少一个周边空腔和布置在所述至少一个周边空腔中的焊料材料以及第二半导体封装，所述第二半导体封装包括至少一个导电柱，其中所述至少一个导电柱电耦合到所述焊料材料 布置在所述至少一个周边空腔中。

公开(公告)号：WO2016081382A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/060932

申请日：2015-11-16

Applicant: QUALCOMM INCORPORATED

Inventor： HWANG, Kyu-Pyung

IPC: H04B10/80 ,  H01L25/16

CPC classification number: H04B10/803 ,  H01L25/167 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H04B10/1143 ,  H01L2924/00

Abstract: Some novel features pertain to a device that includes a first integrated device package and a second integrated device package. The first integrated device package includes a first package substrate, a first integrated device, and a first configurable optical transmitter. The first configurable optical transmitter is configured to be in communication with the first integrated device. The first configurable optical transmitter is configured to transmit an optical beam at a configurable angle. The first configurable optical transmitter includes an optical beam source, an optical beam splitter, and a set of phase shifters coupled to the optical beam splitter. The set of phase shifters is configured to enable the angle at which the optical beam is transmitted. The second integrated device package includes a second package substrate, a second integrated device, and a first optical receiver configured to receive the optical beam from the first configurable optical transmitter.

Abstract translation: 一些新颖的特征涉及包括第一集成器件封装和第二集成器件封装的器件。 第一集成器件封装包括第一封装衬底，第一集成器件和第一可配置光发射器。 第一可配置光发射机被配置为与第一集成设备通信。 第一可配置光发射器被配置为以可配置的角度发送光束。 第一可配置光发射机包括光束源，光束分离器和耦合到光束分离器的一组移相器。 该组移相器被配置为使能够发射光束的角度。 第二集成器件封装包括第二封装衬底，第二集成器件和被配置为从第一可配置光发射器接收光束的第一光接收器。

公开(公告)号：WO2016032900A1

公开(公告)日：2016-03-03

申请号：PCT/US2015/046339

申请日：2015-08-21

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Young Kyu ,  HWANG, Kyu-Pyung

IPC: H01L23/50 ,  H01L23/498

CPC classification number: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248 ,  H01L21/76802 ,  H01L21/7687 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated devices include a substrate, and a capacitor embedded within the substrate. The capacitor is configured to include a first electrode disposed on a first surface, a second electrode disposed on an opposing second surface, and a plurality of capacitor plates extending transverse between the first electrode and the second electrode. Each capacitor plate is electrically coupled to one of the first electrode or the second electrode. A plurality of vias are positioned to extend through the substrate to one of the first electrode or the second electrode. Other aspects, embodiments, and features are also included.

Abstract translation: 集成器件包括衬底和嵌入衬底内的电容器。 电容器被配置为包括设置在第一表面上的第一电极，设置在相对的第二表面上的第二电极和在第一电极和第二电极之间横向延伸的多个电容器板。 每个电容器板电耦合到第一电极或第二电极之一。 定位多个通孔以将基板延伸到第一电极或第二电极中的一个。 还包括其他方面，实施例和特征。

公开(公告)号：WO2015171284A2

公开(公告)日：2015-11-12

申请号：PCT/US2015/026199

申请日：2015-04-16

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Young Kyu ,  HWANG, Kyu-Pyung ,  KIM, Dong Wook ,  ZHANG, Xiaonan ,  LANE, Ryan David

IPC: H01G4/30

CPC classification number: H01G4/236 ,  H01G2/02 ,  H01G2/106 ,  H01G4/224 ,  H01G4/30 ,  H01G4/33 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/115 ,  H05K1/182 ,  H05K1/185 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/10015 ,  Y10T29/42

Abstract: Some novel features pertain to package substrates that include a substrate having an embedded package substrate (EPS) capacitor with equivalent series resistance (ESR) control. The EPS capacitor includes two conductive electrodes separated by a dielectric or insulative thin film material and an equivalent series resistance (ESR) control structure located on top of each electrode connecting the electrodes to vias. The ESR control structure may include a metal layer, a dielectric layer, and a set of metal pillars which are embedded in the set of metal pillars are embedded in the dielectric layer and extend between the electrode and the metal layer. The EPS capacitor having the ESR control structure form an ESR configurable EPS capacitor which can be embedded in package substrates.

Abstract translation: 一些新颖的特征涉及包括具有等效串联电阻（ESR）控制的嵌入式封装衬底（EPS）电容器的衬底的封装衬底。 EPS电容器包括由电介质或绝缘薄膜材料隔开的两个导电电极和位于将电极连接到通孔的每个电极顶部的等效串联电阻（ESR）控制结构。 ESR控制结构可以包括金属层，电介质层和嵌入金属柱组中的一组金属柱，其嵌入电介质层并在电极和金属层之间延伸。 具有ESR控制结构的EPS电容器形成可嵌入封装衬底的ESR可配置EPS电容器。