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    INDUCTOR EMBEDDED IN A PACKAGE SUBTRATE
    1.
    发明公开
    INDUCTOR EMBEDDED IN A PACKAGE SUBTRATE 审中-公开
    在EINEM VERPACKUNGSSUBSTRAT EINGEBETTETER INDUKTOR

    公开(公告)号：EP3123508A1

    公开(公告)日：2017-02-01

    申请号：EP15715112.7

    申请日：2015-03-27

    Applicant: Qualcomm Incorporated

    Inventor： FAZELPOUR, Siamak ,  PAYNTER, Charles David ,  LANE, Ryan David

    IPC: H01L23/498 ,  H01F17/00 ,  H01L23/64 ,  H01L49/02

    CPC classification number: H01F17/0013 ,  H01F2017/002 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011

    Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

    Abstract translation: 一些新颖的特征涉及包括芯层，第一通孔，第一介电层和第一电感器的封装衬底。 芯层包括第一表面和第二表面。 第一个通孔位于核心层。 第一电介质层耦合到芯层的第一表面。 第一电感器位于第一电介质层中。 第一电感器耦合到芯层中的第一通孔。 第一电感器被配置为产生横向穿过封装衬底的磁场。 在一些实施方案中，封装衬底还包括耦合到第一电感器的第一焊盘，其中第一焊盘被配置为耦合到焊球。 在一些实施方案中，封装衬底包括位于芯层中的第二通孔和位于第一介电层中的第二电感器。

    INTEGRATED PASSIVE DEVICE (IPD) ON SUBTRATE
    3.
    发明申请
    INTEGRATED PASSIVE DEVICE (IPD) ON SUBTRATE 审中-公开
    集成无源设备（IPD）

    公开(公告)号：WO2015023696A1

    公开(公告)日：2015-02-19

    申请号：PCT/US2014/050776

    申请日：2014-08-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIM, Daeik Daniel ,  SONG, Young Kyu ,  YUN, Changhan Hobie ,  VELEZ, Mario Francisco ,  ZUO, Chengjie ,  KIM, Jonghae ,  ZHANG, Xiaonan ,  LANE, Ryan David

    IPC: H01L23/498 ,  H01L23/50

    CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

    Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

    Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

    STAGGERED POWER STRUCTURE IN A POWER DISTRIBUTION NETWORK (PDN)
    6.
    发明申请
    STAGGERED POWER STRUCTURE IN A POWER DISTRIBUTION NETWORK (PDN) 审中-公开
    电力分配网络中的分层电力结构（PDN）

    公开(公告)号：WO2015168160A1

    公开(公告)日：2015-11-05

    申请号：PCT/US2015/028061

    申请日：2015-04-28

    Applicant: QUALCOMM INCORPORATED

    Inventor： LANE, Ryan David ,  LI, Yue ,  PAYNTER, Charles David ,  ZANG, Ruey Kae

    IPC: H01L23/50 ,  H01L23/528 ,  H05K1/02

    CPC classification number: H05K1/0216 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/5286 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0236 ,  H05K2201/09309

    Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.

    Abstract translation: 一些新颖的特征涉及包括第一金属层和第二金属层的集成器件。 第一金属层包括第一组区域。 第一组区域包括用于集成设备的配电网络（PDN）的第一网表结构。 第二金属层包括第二组区域。 第二组区域包括集成设备的PDN的第二网表结构。 在一些实现中，第二金属层还包括第三组区域，其包括用于集成设备的PDN的第一网表结构。 在一些实现中，第一金属层包括第三组区域，其包括用于集成设备的PDN的第三网表结构。 第三组区域与第一金属层的第一组区域不重叠。

    INDUCTOR EMBEDDED IN A PACKAGE SUBTRATE
    7.
    发明申请
    INDUCTOR EMBEDDED IN A PACKAGE SUBTRATE 审中-公开
    电感器嵌入在一个封装中

    公开(公告)号：WO2015148996A1

    公开(公告)日：2015-10-01

    申请号：PCT/US2015/023129

    申请日：2015-03-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： FAZELPOUR, Siamak ,  PAYNTER, Charles David ,  LANE, Ryan David

    IPC: H01L23/498 ,  H01F17/00 ,  H01L23/64 ,  H01L49/02

    CPC classification number: H01F17/0013 ,  H01F2017/002 ,  H01F2017/0066 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3011

    Abstract: Some novel features pertain to a package substrate that includes a core layer, a first via, a first dielectric layer, and a first inductor. The core layer includes a first surface and a second surface. The first via is located in the core layer. The first dielectric layer is coupled to the first surface of the core layer. The first inductor is located in the first dielectric layer. The first inductor is coupled to the first via in the core layer. The first inductor is configured to generate a magnetic field that laterally traverses the package substrate. In some implementations, the package substrate further includes a first pad coupled to the first inductor, wherein the first pad is configured to couple to a solder ball. In some implementations, the package substrate includes a second via located in the core layer, and a second inductor located in the first dielectric layer.

    Abstract translation: 一些新颖的特征涉及包括芯层，第一通孔，第一介电层和第一电感器的封装衬底。 芯层包括第一表面和第二表面。 第一个通孔位于核心层。 第一介电层耦合到芯层的第一表面。 第一电感器位于第一电介质层中。 第一电感器耦合到芯层中的第一通孔。 第一电感器被配置为产生横向穿过封装衬底的磁场。 在一些实施方案中，封装衬底还包括耦合到第一电感器的第一焊盘，其中第一焊盘被配置为耦合到焊球。 在一些实施方案中，封装衬底包括位于芯层中的第二通孔和位于第一介电层中的第二电感器。

    TOROID INDUCTOR IN REDISTRIBUTION LAYERS (RDL) OF AN INTEGRATED DEVICE
    8.
    发明申请
    TOROID INDUCTOR IN REDISTRIBUTION LAYERS (RDL) OF AN INTEGRATED DEVICE 审中-公开
    一体化设备的重分布层（RDL）中的电导电感器

    公开(公告)号：WO2015112510A1

    公开(公告)日：2015-07-30

    申请号：PCT/US2015/012090

    申请日：2015-01-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： GU, Shiqun ,  LANE, Ryan David ,  RAY, Urmi

    IPC: H01L23/538 ,  H01L49/02

    CPC classification number: H01L23/5227 ,  H01L21/76838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L28/10 ,  H01L2224/04105 ,  H01L2224/11 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, a first metal redistribution layer coupled to one of the metal layers, and a second metal redistribution layer coupled to the first metal redistribution layer. The first and second metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the integrated device also includes a third metal redistribution layer. The third metal redistribution layer is coupled to the first and second metal redistribution layers. The third metal redistribution layer is a via. In some implementations, the first, second, and third metal redistribution layers are configured to operate as a toroid inductor in the integrated device. In some implementations, the first, second, and third redistribution layers form a set of windings for the toroid inductor.

    Abstract translation: 一些特征涉及集成器件，其包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层，耦合到金属层中的一个的第一金属再分布层，以及耦合到衬底的第二金属再分配层 第一金属再分配层。 第一和第二金属再分布层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，集成器件还包括第三金属再分配层。 第三金属再分布层耦合到第一和第二金属再分配层。 第三金属再分配层是通孔。 在一些实施方案中，第一，第二和第三金属再分配层被配置为在集成器件中作为环形电感器工作。 在一些实施方案中，第一，第二和第三再分配层形成用于环形电感器的一组绕组。

    TOROID INDUCTOR WITH REDUCED ELECTROMAGNETIC FIELD LEAKAGE
    9.
    发明申请
    TOROID INDUCTOR WITH REDUCED ELECTROMAGNETIC FIELD LEAKAGE 审中-公开
    具有降低的电磁场泄漏的环形电感器

    公开(公告)号：WO2017079337A1

    公开(公告)日：2017-05-11

    申请号：PCT/US2016/060168

    申请日：2016-11-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： LI, Yue ,  PAYNTER, Charles David ,  LANE, Ryan David

    IPC: H01F17/00 ,  H01F17/02 ,  H01F27/28

    CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F17/02 ,  H01F27/29 ,  H01F41/041 ,  H01F2027/2809 ,  H05K1/18

    Abstract: A toroid inductor includes a plurality of first turns configured in a first ring shape and a plurality of second turns configured in a second ring shape. The plurality of first turns includes a plurality of first upper interconnects, a plurality of first lower interconnects, and a plurality of first vias coupled to the plurality of first upper interconnects and to the plurality of first lower interconnects. The plurality of second turns is at least partially intertwined with the plurality of first turns. The plurality of second turns includes a plurality of second upper interconnects, a plurality of second lower interconnects, and a plurality of second vias coupled to the plurality of second upper interconnects and to the plurality of second lower interconnects.

    Abstract translation: 环形电感器包括配置成第一环形的多个第一匝和配置成第二环形的多个第二匝。 多个第一匝包括多个第一上互连，多个第一下互连以及耦合到多个第一上互连和多个第一下互连的多个第一通孔。 多个第二匝至少部分地与多个第一匝交织。 所述多个第二匝包括多个第二上互连，多个第二下互连以及耦合到所述多个第二上互连和多个第二下互连的多个第二过孔。

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