SWING TRACKING AND CONTROL
    21.
    发明申请

    公开(公告)号:WO2020205828A1

    公开(公告)日:2020-10-08

    申请号:PCT/US2020/025899

    申请日:2020-03-31

    Abstract: In certain aspects, an apparatus includes a transformer including an input inductor and an output inductor, wherein the input inductor is magnetically coupled to the output inductor. The apparatus also includes a transconductance driver configured to drive the input inductor based on an input signal. The apparatus further includes a feedback circuit configured to detect an output voltage swing at the output inductor, generate a regulated voltage at the input inductor, and control the regulated voltage based on the detected output voltage swing.

    METHOD AND APPARATUS FOR CONCURRENT COMMUNICATION WITH MULTIPLE WIRELESS COMMUNICATION SYSTEMS OF DIFFERENT RADIO ACCESS TECHNOLOGIES
    22.
    发明申请
    METHOD AND APPARATUS FOR CONCURRENT COMMUNICATION WITH MULTIPLE WIRELESS COMMUNICATION SYSTEMS OF DIFFERENT RADIO ACCESS TECHNOLOGIES 审中-公开
    用于不同无线电接入技术的多个无线通信系统的通信通信方法与装置

    公开(公告)号:WO2014204706A2

    公开(公告)日:2014-12-24

    申请号:PCT/US2014/041641

    申请日:2014-06-10

    CPC classification number: H04W88/06 H04B1/0053 H04B1/403 H04W16/14 H04W72/1215

    Abstract: A wireless device supporting concurrent communication with multiple wireless systems of different radio access technologies (RATs) are disclosed. In an exemplary design, an apparatus includes first and second receivers supporting concurrent signal reception from wireless systems of different RATs. The first receiver receives a first downlink signal from a first wireless system of a first RAT. The second receiver receives a second downlink signal from a second wireless system of a second RAT, which is different from the first RAT. The first and second receivers may operate concurrently. The second receiver may be broadband and/or may support carrier aggregation. The apparatus may further include first and second local oscillator (LO) generators to generate LO signals for the first and second receivers, respectively, based on different divider ratios in order to mitigate voltage controlled oscillator (VCO) pulling.

    Abstract translation: 公开了一种支持与不同无线电接入技术(RAT)的多个无线系统的并发通信的无线设备。 在示例性设计中,装置包括支持来自不同RAT的无线系统的并发信号接收的第一和第二接收机。 第一接收机从第一RAT的第一无线系统接收第一下行链路信号。 第二接收机从与第一RAT不同的第二RAT的第二无线系统接收第二下行链路信号。 第一和第二接收器可以同时运行。 第二接收机可以是宽带和/或可以支持载波聚合。 该装置还可以包括第一和第二本地振荡器(LO)发生器,以分别基于不同的分频比产生用于第一和第二接收器的LO信号,以便减轻压控振荡器(VCO)拉动。

    PHASE DETECTION AND CORRECTION FOR A LOCAL OSCILLATOR GENERATOR OPERATING IN A NON-CONTINUOUS MANNER
    23.
    发明申请
    PHASE DETECTION AND CORRECTION FOR A LOCAL OSCILLATOR GENERATOR OPERATING IN A NON-CONTINUOUS MANNER 审中-公开
    本地振荡器发生器在不连续的操作中操作的相位检测和校正

    公开(公告)号:WO2014159083A1

    公开(公告)日:2014-10-02

    申请号:PCT/US2014/021891

    申请日:2014-03-07

    Abstract: Techniques for detecting and correcting phase discontinuity of a local oscillator (LO) signal are disclosed. A wireless device may include an LO generator and a phase detector. The LO generator generates an LO signal used for frequency conversion and is periodically powered on and off. The phase detector detects the phase of the LO signal when the LO generator is powered on. The detected phase of the LO signal is used to identify phase discontinuity of the LO signal. The wireless device may include (i) a single-tone generator that generates a single-tone signal used to detect the phase of the LO signal, (ii) a downconverter that downconverts the single-tone signal with the LO signal and provides a downconverted signal used by the phase detector to detect the phase of LO signal, and (iii) phase corrector that corrects phase discontinuity of the LO signal in the analog domain or digital domain.

    Abstract translation: 公开了用于检测和校正本地振荡器(LO)信号的相位不连续性的技术。 无线设备可以包括LO发生器和相位检测器。 LO发生器产生用于频率转换的LO信号,并且周期性地通电和关断。 当LO发生器通电时,相位检测器检测LO信号的相位。 LO信号的检测相位用于识别LO信号的相位不连续性。 无线设备可以包括(i)生成用于检测LO信号的相位的单音信号的单音发生器,(ii)下变频器,其使用LO信号对单音信号进行下变频并提供下变频 信号由相位检测器使用以检测LO信号的相位,以及(iii)相位校正器,用于校正模拟域或数字域中的LO信号的相位不连续性。

    RECONFIGURABLE LOCAL OSCILLATOR FOR OPTIMAL NOISE PERFORMANCE IN A MULTI-STANDARD TRANSCEIVER
    24.
    发明申请
    RECONFIGURABLE LOCAL OSCILLATOR FOR OPTIMAL NOISE PERFORMANCE IN A MULTI-STANDARD TRANSCEIVER 审中-公开
    可重构的局部振荡器,用于多标准收发器中的最佳噪声性能

    公开(公告)号:WO2012048036A2

    公开(公告)日:2012-04-12

    申请号:PCT/US2011/054974

    申请日:2011-10-05

    Abstract: A transceiver for multi-standard operation (usable, for example, to communicate signals both of a first wireless communication standard and of a second wireless communication standard) has a mixer that receives a local oscillator signal generated by a local oscillator. A PLL of the local oscillator involves a VCO, a digitally programmable analog loop filter, a digitally programmable VCO supply voltage circuit, and a digitally programmable VCO varactor bias control circuit. In one aspect, the bandwidth of the analog loop filter is adjusted depending on the communication standard of the signal being communicated. In other aspects, the VCO supply voltage circuit and/or the varactor bias control circuit are configured in different ways to optimize PLL performance depending on the communication standard of the signal being communicated.

    Abstract translation: 用于多标准操作的收发器(可用于例如传送第一无线通信标准和第二无线通信标准两者的信号)具有混频器,该混频器接收由 本地振荡器。 本地振荡器的PLL涉及VCO,数字可编程模拟环路滤波器,数字可编程VCO电源电压电路和数字可编程VCO变容二极管偏置控制电路。 在一个方面中,模拟环路滤波器的带宽根据所传送信号的通信标准进行调整。 在其他方面,VCO电源电压电路和/或变容二极管偏置控制电路以不同方式配置,以根据所传送信号的通信标准来优化PLL性能。

    REDUCING POWER CONSUMPTION BY TAKING ADVANTAGE OF SUPERIOR IN-CIRCUIT DUPLEXER PERFORMANCE
    25.
    发明申请
    REDUCING POWER CONSUMPTION BY TAKING ADVANTAGE OF SUPERIOR IN-CIRCUIT DUPLEXER PERFORMANCE 审中-公开
    通过获得超级电路双工器性能优势降低功耗

    公开(公告)号:WO2011153076A2

    公开(公告)日:2011-12-08

    申请号:PCT/US2011/038241

    申请日:2011-05-26

    Abstract: Although the duplexer in a full-duplex transceiver circuit may only be guaranteed by the duplexer manufacturer to have a transmit band rejection from its TX port to its RX port of a certain amount, and may only be guaranteed to have a receive band rejection of another amount, the actual transmit band rejection and the actual receive band rejection of a particular instance of the duplexer may be better than specified. Rather than consuming excess power in the receiver and/or transmitter in order to meet performance requirements assuming the duplexer only performs as well as specified, the duplexer's in-circuit performance is measured as part of a transmitter-to-receiver isolation determination. Transmitter and/or receiver power settings are reduced where possible to take advantage of the measured better-than-specified in-circuit duplexer performance, while still meeting transceiver performance requirements. Power settings are not changed during normal transmit and receive mode operation.

    Abstract translation: 虽然全双工收发器电路中的双工器可能只能由双工器制造商保证从其TX端口到其一定数量的RX端口的发射波段抑制,并且只能保证具有另一个的接收频带抑制 数量,双工器的特定实例的实际发射频带抑制和实际接收频带抑制可能优于指定的。 假设双工器仅执行指定,而不是在接收机和/或发射机中消耗多余的功率,以满足性能要求,则双工器的在线性能是作为发射机到接收机隔离确定的一部分进行测量的。 发射机和/或接收机功率设置在可能的情况下可以减少,以便在仍然满足收发器性能要求的同时利用测得的优于指定的在线双工器性能。 在正常的发送和接收模式操作期间,电源设置不会改变。

    DUTY CYCLE ADJUSTMENT FOR A LOCAL OSCILLATOR SIGNAL
    26.
    发明申请
    DUTY CYCLE ADJUSTMENT FOR A LOCAL OSCILLATOR SIGNAL 审中-公开
    用于本地振荡器信号的占空比调整

    公开(公告)号:WO2010068503A1

    公开(公告)日:2010-06-17

    申请号:PCT/US2009/065961

    申请日:2009-11-25

    CPC classification number: H03K5/1565 H03K3/017 H03L7/08

    Abstract: A local oscillator (LO) module comprises a local oscillator and a feedback circuit. The local oscillator, biased at a supply voltage, generates a local oscillator signal having a duty cycle. The feedback circuit makes an absolute adjustment of the duty cycle of the local oscillator signal in response to a difference between a first voltage signal, representing a voltage level of the local oscillator signal, and a second voltage signal, representing a voltage level of a portion of the supply voltage corresponding to a desired duty cycle for the local oscillator signal.

    Abstract translation: 本地振荡器(LO)模块包括本地振荡器和反馈电路。 以电源电压偏置的本地振荡器产生具有占空比的本地振荡器信号。 响应于表示本地振荡器信号的电压电平的第一电压信号和表示本地振荡器信号的电压电平的第二电压信号之间的差异,反馈电路对本地振荡器信号的占空比进行绝对调整, 的电源电压对应于本地振荡器信号的期望占空比。

    MIXER ARCHITECTURES
    27.
    发明申请
    MIXER ARCHITECTURES 审中-公开
    混合器架构

    公开(公告)号:WO2010062702A2

    公开(公告)日:2010-06-03

    申请号:PCT/US2009/062867

    申请日:2009-10-30

    CPC classification number: H03D7/1441 H03D7/1433 H03D7/1466 H03D2200/0043

    Abstract: Techniques for designing a single-balanced mixer coupled to a dummy portion with a dummy load to improve noise rejection. In an aspect, a single-ended signal (RF) from a stage preceding the mixer, e.g., a low-noise amplifier (LNA), is coupled to the input of the single-balanced mixer to be mixed with a local oscillator (LO) signal. A dummy portion replicating the topology of the single-balanced mixer is coupled to the single-balanced mixer to improve noise rejection, with the LO signal also provided to the dummy portion. The input of the dummy portion may be coupled, e.g., to a dummy load, which is designed to replicate the loading characteristics of the preceding stage, e.g., the LNA.

    Abstract translation: 用于设计耦合到具有虚拟负载的虚拟部分以改善噪声抑制的单平衡混频器的技术 在一个方面,来自混频器之前的级(例如低噪声放大器(LNA))的单端信号(RF)耦合到单平衡混频器的输入端以与本地振荡器(LO )信号。 复制单平衡混频器的拓扑结构的虚拟部分耦合到单平衡混频器以改善噪声抑制,LO信号也提供给虚拟部分。 虚设部分的输入可以例如耦合到虚设负载,虚设负载被设计为复制前级的负载特性,例如LNA。

    MILLIMETER WAVE ANTENNA TUNER
    28.
    发明申请

    公开(公告)号:WO2023048927A1

    公开(公告)日:2023-03-30

    申请号:PCT/US2022/042435

    申请日:2022-09-02

    Abstract: Designs and techniques for manufacturing microelectronic antenna tuners are provided. An example microelectronic antenna system includes a radio frequency integrated circuit comprising a plurality of radio frequency signal ports disposed in a first area, a plurality of tuning devices disposed in a second area of the radio frequency integrated circuit, at least one antenna element disposed on a substrate coupled to the radio frequency integrated circuit, and at least one feedline disposed in the substrate and configured to communicatively couple the at least one antenna element, at least one of the plurality of tuning devices, and one of the plurality of radio frequency signal ports.

    PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES
    29.
    发明申请
    PSEUDO-CML LATCH AND DIVIDER HAVING REDUCED CHARGE SHARING BETWEEN OUTPUT NODES 审中-公开
    PSEUDO-CML LATCH和DIVIDER在输出节点之间具有减少的充电共享

    公开(公告)号:WO2014209716A1

    公开(公告)日:2014-12-31

    申请号:PCT/US2014/042935

    申请日:2014-06-18

    CPC classification number: H03K3/017 H01L21/823871 H03K3/356121 H03K3/356139

    Abstract: In one example, a high-speed divider (38) includes two identical pseudo-CML latches (L1, L2) and four output inverters (70-73). Each latch includes a pair of cross-coupled signal holding transistors (MN1, MN2, MN7, MN8). A first P-channel pull-up circuit (MP1, MP3) pulls up on a second output node QB of the latch. A second P-channel pull-up circuit (MP2, MP4) pulls up on a first output node Q of the latch. A pull-down circuit (MN3-5, MN9-11) involves four N-channel transistors. This pull-down circuit: 1) couples the QB node to ground when a clock signal CK is high and a data signal D is high, 2) couples the Q node to ground when CK is high and D is low, 3) prevents a transfer of charge between the QB and Q nodes through the pull-down circuit when D transitions during a time period when CK is low, and 4) decouples the QB and Q nodes from the pull-down circuit when CK is low.

    Abstract translation: 在一个示例中,高速分配器(38)包括两个相同的伪CML锁存器(L1,L2)和四个输出反相器(70-73)。 每个锁存器包括一对交叉耦合的信号保持晶体管(MN1,MN2,MN7,MN8)。 第一个P通道上拉电路(MP1,MP3)在锁存器的第二个输出节点QB上拉起。 第二个P沟道上拉电路(MP2,MP4)在锁存器的第一个输出节点Q上拉起。 下拉电路(MN3-5,MN9-11)涉及四个N沟道晶体管。 该下拉电路:1)当时钟信号CK为高电平且数据信号D为高电平时,将QB节点耦合到地,2)当CK为高电平且D为低电平时将Q节点接地,3)防止 当CK为低电平时,D转换时,通过下拉电路在QB和Q节点之间传输电荷;以及4)当CK为低电平时,将QB和Q节点与下拉电路解耦。

    CURRENT-MODE BUFFER WITH OUTPUT SWING DETECTOR FOR HIGH FREQUENCY CLOCK INTERCONNECT
    30.
    发明申请
    CURRENT-MODE BUFFER WITH OUTPUT SWING DETECTOR FOR HIGH FREQUENCY CLOCK INTERCONNECT 审中-公开
    具有高频时钟互联的输出开关检测器的电流模式缓冲器

    公开(公告)号:WO2014150581A1

    公开(公告)日:2014-09-25

    申请号:PCT/US2014/023684

    申请日:2014-03-11

    CPC classification number: H03K5/08 H03K6/02

    Abstract: A high-speed current-mode clock driver includes feedback circuitry to maintain the voltage swing of a biasing node within a defined range. The current-mode clock driver includes a PMOS and an NMOS transistor receiving an oscillating signal at their gate terminals. The drain terminals of the PMOS and NMOS transistors are respectively coupled to input terminals of first and second variable conductivity circuits whose output terminals are coupled to a common node. A control circuit increases the conductivities of the first and second variable conductivity circuits in response to decreases in voltage swing of the common node, and decreases the conductivities of the first and second variable conductivity circuits in response to increases in voltage swing of the common node. The first and second variable conductivity circuits are optionally PMOS and NMOS transistors respectively.

    Abstract translation: 高速电流模式时钟驱动器包括反馈电路,以将偏置节点的电压摆幅保持在限定的范围内。 电流模式时钟驱动器包括在其栅极端子处接收振荡信号的PMOS和NMOS晶体管。 PMOS和NMOS晶体管的漏极端子分别耦合到第一和第二可变电导率电路的输入端,其输出端耦合到公共节点。 控制电路响应于公共节点的电压摆幅的减小而增加第一和第二可变电导率电路的电导率,并且响应于公共节点的电压摆幅的增加而降低第一和第二可变电导率电路的电导率。 第一和第二可变电导率电路分别是PMOS和NMOS晶体管。

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