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公开(公告)号：WO2023049617A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/075771
申请日：2022-08-31
Applicant: QUALCOMM INCORPORATED
Inventor： LEE, Jang Joon , HOLLAND, Kyle David , KANG, Jian , TASIC, Aleksandar Miodrag , LIAO, Chih-Fan , LI, Yingying , LEUNG, Lai Kan , NARATHONG, Chiewcharn
IPC: H04B1/08
Abstract: Embodiments of this disclosure may include a receiver with a reconfigurable processing path for different signal conditions. Such a receiver may reconfigure between a mixer-first configuration and an amplifier-first configuration. In the mixer-first configuration, an RF input signal is not passed through an LNA for amplification before processing the RF input signal for downconversion to baseband and eventual extraction of the information in the signal. In the amplifier-first configuration, an RF input signal is passed through an LNA for amplification before processing the RF input signal for downconversion to baseband and eventual extraction of the information in the signal. Reconfiguring the receiver between mixer-first and amplifier-first configurations may be performed based on detection of jammer signals and/or measurement of signal-to-noise ratio (SNR).
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公开(公告)号：WO2022132401A2
公开(公告)日：2022-06-23
申请号：PCT/US2021/060374
申请日：2021-11-22
Applicant: QUALCOMM INCORPORATED
Inventor： LEUNG, Lai Kan , TASIC, Aleksandar Miodrag , GATTA, Francesco , NARATHONG, Chiewcharn , HOLLAND, Kyle David
IPC: H04B1/10 , H03F2200/294 , H03F2200/451 , H03F3/19 , H03M1/12 , H04B1/1027 , H04B1/109 , H04K3/22
Abstract: The disclosure relates to an apparatus including a receiver configured to process a radio frequency (RF) signal to generate a baseband signal; a radio frequency (RF) jammer detector configured to generate a signal indicative of whether an RF jammer is present at an input of the receiver; and a receiver bias circuit configured to generate a supply voltage for the receiver based on the RF jammer indication signal. In another aspect, the apparatus includes constant gain bias circuit to maintain the gain of the receiver constant in response to changes in the supply voltage. In other aspects, the receiver bias circuit may suspend the generating of the supply voltage based on the RF jammer indication signal if the power level of the target received signal is above a threshold. In other aspects, the receiver bias circuit changes the supply voltage during cyclic prefix (CP) intervals between downlink intervals.
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公开(公告)号：WO2016178794A1
公开(公告)日：2016-11-10
申请号：PCT/US2016/026679
申请日：2016-04-08
Applicant: QUALCOMM INCORPORATED
Inventor： LEUNG, Lai Kan , WANG, Kevin Hsi Huai , PAN, Dongling , NARATHONG, Chiewcharn
CPC classification number: H04B17/21 , H03F1/0205 , H03F1/0277 , H03F3/189 , H03F3/19 , H03F3/211 , H03F3/24 , H03F3/62 , H03F3/68 , H03F3/72 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2203/21106 , H03F2203/21142 , H03F2203/21145 , H04W24/02
Abstract: An amplifier module (600) with an output coupler (640) is disclosed. The amplifier module (600) may include a plurality of input terminals (601-605) and two or more output terminals (610, 611). Each input terminal may be coupled to an input of an independent amplifier (620-624). Outputs from the independent amplifiers (620-624) may be coupled to the two or more output terminals (610, 611). The amplifier module (600) may include an output coupler (640) to couple the two or more output terminals (610, 611) together. A signal may be received by a first output terminal (610) and be coupled by the output coupler (640) to a second output terminal (611). In some embodiments, when the two or more output terminals (610, 611) are coupled together, the independent amplifiers (620-624) may be made inactive or operated in a minimum gain configuration.
Abstract translation: 公开了具有输出耦合器（640）的放大器模块（600）。 放大器模块（600）可以包括多个输入端子（601-605）和两个或更多个输出端子（610,611）。 每个输入端可以耦合到独立放大器（620-624）的输入端。 来自独立放大器（620-624）的输出可以耦合到两个或更多个输出端子（610,611）。 放大器模块（600）可以包括将两个或更多个输出端子（610,611）耦合在一起的输出耦合器（640）。 信号可以由第一输出端子（610）接收并由输出耦合器（640）耦合到第二输出端子（611）。 在一些实施例中，当两个或多个输出端子（610,611）耦合在一起时，独立放大器（620-624）可以使其处于非活动状态或以最小增益配置运行。
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公开(公告)号：WO2015183478A1
公开(公告)日：2015-12-03
申请号：PCT/US2015/029067
申请日：2015-05-04
Applicant: QUALCOMM INCORPORATED
Inventor： NARATHONG, Chiewcharn , LEUNG, Lai Kan , PAN, Dongling , RANGARAJAN, Rajagopalan , WANG, Kevin Hsi-huai , ASURI, Bhushan Shanti , TANG, Yiwu
CPC classification number: H04J4/00 , H04B1/0082 , H04B1/3833 , H04B1/403 , H04B1/50 , H04B1/54 , H04B7/00 , H04L5/001 , H04L5/0023 , H04L5/14 , H04L5/1469 , H04L7/00 , H04L27/36 , H04L27/38 , H04W88/02
Abstract: Reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method including: connecting a first frequency synthesizer to a first CA Tx chain; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain.
Abstract translation: 使用多个频率合成器和多个载波聚合（CA）接收机（Rx）和发射机（Tx）链重新配置收发器设计，所述方法包括：将第一频率合成器连接到第一CA Tx链; 将多个频率合成器连接到多个CA Rx链，其中多个频率合成器中的第二频率合成器作为共享合成器连接到第一CA Rx链和第二CA Tx链。
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5.发明申请MULTI-WAY DIVERSITY RECEIVER WITH MULTIPLE SYNTHESIZERS IN A CARRIER AGGREGATION TRANSCEIVER 审中-公开多方位接收器与多个合成器在载波聚合收发器
公开(公告)号：WO2015175109A1
公开(公告)日：2015-11-19
申请号：PCT/US2015/024189
申请日：2015-04-03
Applicant: QUALCOMM INCORPORATED
Inventor： LEUNG, Lai Kan , NARATHONG, Chiewcharn , RANGARAJAN, Rajagopalan , PAN, Dongling , TANG, Yiwu , TASIC, Aleksandar Miodrag
IPC: H04B1/00
CPC classification number: H04B7/0897 , H04B1/0082 , H04B1/16 , H04L27/152
Abstract: Certain aspects of the present disclosure provide multi-way diversity receivers with multiple synthesizers. Such a multi-way diversity receiver may be implemented in a carrier aggregation (CA) transceiver. One example wireless reception diversity circuit generally includes three or more receive paths for processing received signals and two or more frequency synthesizing circuits configured to generate local oscillating signals to downconvert the received signals. Each of the frequency synthesizing circuits is shared by at most two of the receive paths, and each pair of the frequency synthesizing circuits may generate a pair of local oscillating signals having the same frequency.
Abstract translation: 本公开的某些方面提供具有多个合成器的多路分集接收机。 这种多路分集接收机可以在载波聚合（CA）收发机中实现。 一个示例性的无线接收分集电路通常包括用于处理接收信号的三个或更多个接收路径和被配置为产生本地振荡信号以下变频接收信号的两个或多个频率合成电路。 每个频率合成电路由至多两个接收路径共享，并且每对频率合成电路可以产生具有相同频率的一对本地振荡信号。
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Patent Agency Ranking
公开(公告)号：WO2015175094A1
公开(公告)日：2015-11-19
申请号：PCT/US2015/022055
申请日：2015-03-23
Applicant: QUALCOMM INCORPORATED
Inventor： TASIC, Aleksandar Miodrag , NARATHONG, Chiewcharn , HOLENSTEIN, Christian , PAN, Dongling , TANG, Yiwu , RANGARAJAN, Rajagopalan , LEUNG, Lai Kan
CPC classification number: H04L27/2653 , H03F1/223 , H03F3/193 , H03F3/245 , H04B1/0064 , H04L45/16 , H04L45/245
Abstract: Multiplex modules for use in carrier aggregation receivers are disclosed. In an exemplary embodiment, an apparatus includes an LNA multiplexer configured to receive a plurality of RF signals at a plurality of input terminals and to combine the RF signals into a combined RF signal that is output from an output terminal. The apparatus also includes an LNA demultiplexer configured to receive the combined RF signal at an input port that is connected to the output terminal and to distribute the combined RF signal to a plurality of output ports.
Abstract translation: 公开了用于载波聚合接收机的多路复用模块。 在示例性实施例中，一种装置包括LNA多路复用器，其被配置为在多个输入端子处接收多个RF信号，并将RF信号组合成从输出端输出的组合RF信号。 该装置还包括LNA解复用器，其被配置为在连接到输出端子的输入端口处接收组合的RF信号，并将组合的RF信号分配到多个输出端口。
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公开(公告)号：WO2012048034A2
公开(公告)日：2012-04-12
申请号：PCT/US2011/054971
申请日：2011-10-05
Applicant: QUALCOMM INCORPORATED , LIU, Li , NARATHONG, Chiewcharn
Inventor： LIU, Li , NARATHONG, Chiewcharn
CPC classification number: H03L1/025 , H03B5/04 , H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B5/1265 , H03L1/023 , H03L7/099 , H03L7/104 , H03L7/1976
Abstract: A resonator of a VCO includes a fine tuning main varactor circuit, an auxiliary varactor circuit, and a coarse tuning capacitor bank circuit coupled in parallel with an inductance. The main varactor circuit includes a plurality of circuit portions that can be separately disabled. Within each circuit portion is a multiplexing circuit that supplies a selectable one of either a fine tuning control signal (FTAVCS) or a temperature compensation control signal (TCAVCS) onto a varactor control node within the circuit portion. If the circuit portion is enabled then the FTAVCS is supplied onto the control node so that the circuit portion is used for fine tuning. If the circuit portion is disabled then the TCAVCS is supplied onto the control node so that the circuit portion is used to combat VCO frequency drift as a function of temperature. How the voltage of the TCAVCS varies with temperature is digitally programmable.
Abstract translation: VCO的谐振器包括与电感并联耦合的微调主变容管电路，辅助变容管电路和粗调电容器组电路。 主变容管电路包括可以单独禁用的多个电路部分。 在每个电路部分内的是一个多路复用电路，该电路把微调控制信号（FTAVCS）或温度补偿控制信号（TCAVCS）中的可选一个提供到电路部分内的变容二极管控制节点上。 如果电路部分被启用，则将FTAVCS提供给控制节点，使得电路部分用于微调。 如果电路部分被禁止，则TCAVCS被提供到控制节点上，使得电路部分被用于对抗作为温度的函数的VCO频率漂移。 TCAVCS的电压如何随温度变化而变化，是数字可编程的。
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公开(公告)号：WO2010019607A1
公开(公告)日：2010-02-18
申请号：PCT/US2009/053460
申请日：2009-08-11
Applicant: QUALCOMM INCORPORATED , NARATHONG, Chiewcharn , ANIRUDDHAN, Sankaran
Inventor： NARATHONG, Chiewcharn , ANIRUDDHAN, Sankaran
CPC classification number: H03F1/565 , H03F1/42 , H03F3/195 , H03F3/245 , H03F3/72 , H03F2200/06 , H03F2200/294 , H03F2200/36 , H03F2200/451 , H03F2200/489 , H03F2200/534 , H03F2203/7203 , H03H7/42
Abstract: Techniques for improving the quality factor ("Q") of a balun in the presence of loading stages are disclosed. In an exemplary embodiment, the ground node (101,2b) of a balun secondary (single-ended) element (101) is connected to a source node (200b) of an amplifier stage (200) via a common ground node (300a). The connection may be made physically short to minimize any parasitic elements. In another exemplary embodiment, the common ground node (300a)may be coupled to an off-chip ground voltage via a peaking inductor ( (300). The peaking inductor (300) may be implemented on-chiρ, e.g., as a spiral inductor, or off-chip e.g., using bondwires.
Abstract translation: 披露了在负载阶段存在下改善平衡不平衡转换器的品质因数（“Q”）的技术。 在示例性实施例中，平衡不平衡变压器次级（单端）元件（101）的接地节点（101,2b）经由公共接地节点（300a）连接到放大器级（200）的源节点（200b） 。 连接可以在物理上短，以最小化任何寄生元件。 在另一示例性实施例中，公共接地节点（300a）可以通过峰值电感器（300）耦合到片外接地电压。峰值电感器（300）可以被实现为例如螺旋 电感器或芯片外，例如，使用键合线。
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公开(公告)号：WO2008002792A3
公开(公告)日：2008-01-03
申请号：PCT/US2007/071496
申请日：2007-06-18
Applicant: QUALCOMM INCORPORATED , NARATHONG, Chiewcharn , SU, Wenjun
Inventor： NARATHONG, Chiewcharn , SU, Wenjun
IPC: H03K3/356 , H03K19/017 , H03K19/0185
Abstract: Differential signal output nodes of a CML buffer (102) are DC-coupled by contiguous conductors to the differential signal input nodes of a load (105) (for example, a CML logic element). The CML buffer (102) includes a pulldown load latch (112) that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load (105), thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.
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公开(公告)号：WO2023049616A1
公开(公告)日：2023-03-30
申请号：PCT/US2022/075764
申请日：2022-08-31
Applicant: QUALCOMM INCORPORATED
Inventor： HOLLAND, Kyle David , LEE, Jang Joon , KODKANI, Rahul , TASIC, Aleksandar Miodrag , LIAO, Chih-Fan , LEUNG, Lai Kan , NARATHONG, Chiewcharn
Abstract: An amplifier (320) may include multiple stages (322, 324), with the multiple stages (322, 324) arranged in a fan-out configuration. The fan-out configuration provides multiple amplified signals at multiple amplifier output nodes, which may be coupled to a shared set of downconverters (330A, 330B, 330C). The shared downconverters (330A, 330B, 330C) may support processing of only a smaller bandwidth than the largest possible bandwidth of an input RF signal input to the amplifier (320). For example, the downconverters may support a bandwidth matching a smallest bandwidth of a supported RF signal. For example, when the amplifier (320) is intended to support 5G mmWave RF signals and 5G sub-6 GHz RF signals, the downconverters (330A, 330B, 330C) may each individually support a bandwidth of carriers in the 5G sub-6 GHz RF signals but not individually support the entire bandwidth of a possible 5G mmWave RF signal.
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