公开(公告)号：WO2009152105A2

公开(公告)日：2009-12-17

申请号：PCT/US2009/046642

申请日：2009-06-08

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo ,  BALLANTYNE, Gary John ,  RANGARAJAN, Rajagopalan

Inventor： SUN, Bo ,  BALLANTYNE, Gary John ,  RANGARAJAN, Rajagopalan

IPC: H03L7/099 ,  H04B1/04 ,  H04B1/16

CPC classification number: H03L7/099 ,  H03L2207/06

Abstract: Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed.

Abstract translation: 公开了用于校准数字控制振荡器（DCO）的技术。 在本公开的一方面，确定用于操作DCO的初始控制代码集。 识别从初始集合产生的输出频率范围。 在频率范围内识别重叠的间隙或实例。 对于重叠情况，从与重叠实例相对应的初始集中移除控制代码以建立修订集。 对于间隙情况，将控制代码添加到初始设置中，以产生填充间隙的频率值。 还公开了一种用于执行该装置的装置。

公开(公告)号：WO2009111491A1

公开(公告)日：2009-09-11

申请号：PCT/US2009/035908

申请日：2009-03-03

Applicant: QUALCOMM INCORPORATED ,  SUN, Bo ,  YANG, Zixiang

Inventor： SUN, Bo ,  YANG, Zixiang

IPC: H03M1/50

CPC classification number: G04F10/005

Abstract: Techniques for enabling a time-to-digital converter (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.

Abstract translation: 公开了一种能够使时间数字转换器（TDC）采用次逆变器延迟分辨率进行采样的技术。 在一个实施例中，TDC中的差分D-Q触发器的输入被耦合到单端信号和该信号的延迟和反相版本，以允许信号的时间插值。 进一步公开的是平衡TDC内的第一延迟线和互补延迟线的负载的技术。

公开(公告)号：WO2009088790A1

公开(公告)日：2009-07-16

申请号：PCT/US2008/088263

申请日：2008-12-24

Applicant: QUALCOMM Incorporated ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh ,  YANG, Zixiang

Inventor： SUN, Bo ,  SAHOTA, Gurkanwal Singh ,  YANG, Zixiang

IPC: H03L7/08 ,  H03L7/087

CPC classification number: H03L7/0802 ,  H03L7/087

Abstract: A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

Abstract translation: 数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。 定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。 控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。 在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号 以获得TDC的第一个时钟信号。

公开(公告)号：WO2009073580A2

公开(公告)日：2009-06-11

申请号：PCT/US2008/085084

申请日：2008-11-29

Applicant: QUALCOMM INCORPORATED ,  BALLANTYNE, Gary John ,  SUN, Bo

Inventor： BALLANTYNE, Gary John ,  SUN, Bo

IPC: H03L7/085

CPC classification number: H03L7/10 ,  H03L7/085 ,  H03L7/087 ,  H03L2207/50

Abstract: In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal.

Abstract translation: 在一个方面，数字PLL（DPLL）基于输入和输出相位的小数部分进行操作。 DPLL累加至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差（例如使用时间 - 数字转换器（TDC））来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分确定相位误差。 DPLL然后基于相位误差产生振荡器的控制信号。 在另一方面，DPLL包括合成的累加器，其通过基于参考信号跟踪振荡器信号周期的数量来确定粗略的输出相位。

公开(公告)号：WO2009039444A1

公开(公告)日：2009-03-26

申请号：PCT/US2008/077121

申请日：2008-09-19

Applicant: QUALCOMM INCORPORATED ,  SEE, Puay Hoe Andrew ,  SAHOTA, Gurkanwal Singh ,  SUN, Bo ,  BALLANTYNE, Gary, John ,  PANTON, William, Ronald ,  CHOI, Zae Yong

Inventor： SEE, Puay Hoe Andrew ,  SAHOTA, Gurkanwal Singh ,  SUN, Bo ,  BALLANTYNE, Gary, John ,  PANTON, William, Ronald ,  CHOI, Zae Yong

IPC: H04L27/00 ,  H04L27/36 ,  H04B1/00

CPC classification number: H04L27/0008 ,  H03C3/0916 ,  H03C3/0975 ,  H03C5/00 ,  H03F1/3241 ,  H03F1/3252 ,  H04B1/0483 ,  H04B2001/0425 ,  H04L27/361 ,  H04L27/362

Abstract: Transmitters supporting multiple modulation modes and/or multiple frequency bands are described. A transmitter may perform large signal polar modulation, small signal polar modulation, and/or quadrature modulation, which may support different modulation schemes and systems. Circuit blocks may be shared by the different modulation modes to reduce cost and power. For example, a single modulator (160) and a single power amplifier (170) may be used for small signal polar modulation and quadrature modulation. The transmitter may apply pre-distortion (124,142) to improve performance, to allow a power amplifier to support multiple frequency bands, to allow the power amplifier to operate at higher output power levels, etc. Envelope and phase distortions due to non-linearity of the power amplifier may be characterized for different input levels and different bands and stored at the transmitter. Thereafter, envelope and phase signals may be pre-distorted based on the stored characterizations to compensate for non-linearity of the power amplifier.

Abstract translation: 描述了支持多个调制模式和/或多个频带的发射机。 发射机可以执行大信号极性调制，小信号极化调制和/或正交调制，其可以支持不同的调制方案和系统。 电路块可以由不同的调制模式共享以降低成本和功率。 例如，单个调制器（160）和单个功率放大器（170）可用于小信号极性调制和正交调制。 发射机可以应用预失真（124,142）来提高性能，以允许功率放大器支持多个频带，以允许功率放大器在较高的输出功率电平下工作等。由于非线性的包络和相位失真 功率放大器可以被表征为不同的输入电平和不同的频带并存储在发射机。 此后，包络和相位信号可以基于存储的特征来预失真，以补偿功率放大器的非线性。

公开(公告)号：WO2008157295A1

公开(公告)日：2008-12-24

申请号：PCT/US2008/066839

申请日：2008-06-13

Applicant: QUALCOMM Incorporated ,  SEO, Dongwon ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh (Kamal) ,  MISHRA, Manu

Inventor： SEO, Dongwon ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh (Kamal) ,  MISHRA, Manu

IPC: H03M1/00

CPC classification number: H03M1/002 ,  H03M1/682 ,  H03M1/747

Abstract: A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.

Abstract translation: 公开了用于将具有最高有效位的集合M的N位的数字信号和最低有效位的集合L转换为模拟信号的数模转换器，RF发送信道和方法。 数字信号定义了一组编码值，它们被转换为模拟值并被调制到RF信号上。 数模转换器包括多个开关和输出级，用于至少提供第一差分输出信号和第二差分输出信号。 输出级修改从多个开关接收的电流，使得第一和第二差分输出信号的平均输出电流的值被转向在编码值的中点处的相对低的电流值。

公开(公告)号：WO2023048957A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/042939

申请日：2022-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： YE, Jianwen ,  SUN, Bo ,  ZHONG, Cheng

IPC: H03L7/081 ,  H03L7/24

Abstract: A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

公开(公告)号：WO2021076278A1

公开(公告)日：2021-04-22

申请号：PCT/US2020/051958

申请日：2020-09-22

Applicant: QUALCOMM INCORPORATED

Inventor： PARK, Joung Won ,  SUN, Bo

IPC: H03F3/45 ,  H03G3/30 ,  H03G5/28 ,  H04L25/03 ,  H03G1/00

Abstract: In certain aspects, an amplifier (605) includes a first transistor (415) including a gate, a drain, and a source, wherein the gate of the first transistor (415) is coupled to a first input (412) of the amplifier (605). The amplifier (605) also includes a second transistor (418) including a gate, a drain, and a source, wherein the gate of the second transistor (418) is coupled to a second input (414) of the amplifier (605). The amplifier (605) further includes a first signal path (615) coupled between the first input (412) of the amplifier (605) and the source of the second transistor (418), a second signal path (618) coupled between the second input (414) of the amplifier (605) and the source of the first transistor (415), a first load coupled to the drain of the first transistor (415), and a second load coupled to the drain of the second transistor (418).

公开(公告)号：WO2017189160A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/025171

申请日：2017-03-30

Applicant: QUALCOMM INCORPORATED

Inventor： ZANUSO, Marco ,  MARUCCI, Giovanni ,  HUNG, Tsai-Pi ,  GATTA, Francesco ,  SUN, Bo

IPC: H04B1/713 ,  H03L7/197 ,  H03L7/08

CPC classification number: H04L7/0331 ,  H03L7/08 ,  H03L7/087 ,  H03L7/099 ,  H03L7/113 ,  H03L7/1974 ,  H03L7/1976 ,  H03L2207/06 ,  H04B1/40 ,  H04B1/713 ,  H04B2201/71353 ,  H04W72/0453

Abstract: A fast frequency hopping implementation in a phase lock loop (PLL) circuit achieves a PLL lock to a new frequency in a very short period of time. In one instant, frequency allocation at a transceiver is changed. In response, a local oscillator frequency hops to a new center frequency based on the changed frequency allocation. The hopping to the new center frequency is based on two-point modulation of a phase locked loop.

Abstract translation: 锁相环（PLL）电路中的快速跳频实现在很短的时间内实现了PLL锁定到新的频率。 在一个瞬间，收发器处的频率分配被改变。 作为响应，基于改变的频率分配，本地振荡器频率跳跃到新的中心频率。 跳到新的中心频率是基于锁相环的两点调制。

公开(公告)号：WO2015041880A1

公开(公告)日：2015-03-26

申请号：PCT/US2014/054519

申请日：2014-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： BUTTERFIELD, Daniel Keyes ,  VERMA, Sumit ,  DUNWORTH, Jeremy Darren ,  SUN, Bo

IPC: H04B1/04 ,  H03M3/00

CPC classification number: H03M1/1245 ,  H03M3/344 ,  H03M3/504 ,  H04B1/0007 ,  H04B1/04 ,  H04B1/38

Abstract: A transmitter includes a delta-sigma modulator (100) characterized by a noise transfer function having a multitude of zeroes positioned substantially near a frequency band of a receive signal. The transmitter further includes, in part, a multi-phase digital-to-analog converter, DAC (200), converting an output signal of the delta- sigma modulator to an analog signal. The DAC is characterized by a transfer function that passes the desired signal to its output and attenuates a multitude of images of the sampling clock signal. The transmitter transmits at a frequency defined by an odd multiple of a fraction of the sampling clock signal frequency. The DAC includes a number of stages each pair of which is associated with one of the images being attenuated. The delta-sigma modulator includes a multitude of stages each associated with a different one of the zeroes. Each stage of said delta-sigma modulator optionally receives three tap coefficients.

Abstract translation: 发射机包括Δ-Σ调制器（100），其特征在于噪声传递函数具有基本上接近接收信号的频带的多个零点。 发射机还部分地包括将Δ-Σ调制器的输出信号转换为模拟信号的多相数模转换器DAC（200）。 DAC的特征在于将所需信号传递到其输出并衰减采样时钟信号的大量图像的传递函数。 发射机以由采样时钟信号频率的一部分的奇数倍定义的频率发射。 DAC包括多个阶段，每个阶段与被衰减的图像中的一个相关联。 Δ-Σ调制器包括多个级，其各自与不同的一个零相关联。 所述Δ-Σ调制器的每个级可任选地接收三个抽头系数。