公开(公告)号：JPH0472764A

公开(公告)日：1992-03-06

申请号：JP18564990

申请日：1990-07-13

Applicant: SHARP KK

Inventor： KAWANABE HITOSHI ,  KOYAMA JUNICHIRO ,  NAKAYAMA TAIAN ,  IMANAKA HIDEYUKI ,  KONISHI TOKUO

IPC: H01L29/43 ,  H01L21/28

Abstract: PURPOSE:To obtain an electrode excellent in adhesion and to realize a soldering process excellent and stable by a method wherein an aluminum layer serving as a silicon oxide reducing layer, a molybdenum layer serving as a mix preventing layer, a nickel layer, and a silver layer are successively formed on the surface of a silicon semiconductor substrate through vapor deposition, and the laminate concerned is sintered through a thermal treatment. CONSTITUTION:The rear side of a silicon semiconductor substrate 1 is cleaned though a chemical treatment, and a first aluminum layer 2 is vapor deposited. Then, a second molybdenum layer 3, a third nickel layer 4, and a fourth silver layer 5 are vapor deposited. An electron beam evaporation method is utilized to vapor deposit these layers. Lastly, the vapor deposited layers are thermally treated at a temperature of 200-570 deg.C in a nitrogen atmosphere. By this heat treatment, the vapor deposited particles are sintered. Lastly, the sintered layers are split into chips through dicing and packaged.

公开(公告)号：JPH0371639A

公开(公告)日：1991-03-27

申请号：JP20899889

申请日：1989-08-10

Applicant: SHARP KK

Inventor： KOYAMA JUNICHIRO

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/732

Abstract: PURPOSE:To shorten the switching time of a transistor by a method wherein high-concentration regions are provided in a base diffused region at the lower parts of the contact parts between base electrodes and the base diffused region. CONSTITUTION:High-concentration regions 4 are provided in a base diffused region at the lower parts of base electrode contact parts 10 between base electrodes 5, 5 and the base diffused region 1. First, a high-concentration impurity to give a second conductivity type is diffused in parts of scheduled base regions in the surface on one side of a first conductivity type silicon substrate to form high-concentration regions 4. Then, an impurity is diffused by heat treatment to form a second conductivity type base diffused region 1. The silicon substrate on the outside of the region 1 is used as a collector region 3. Then, a first conductivity type impurity is diffused in a part of the surface of the region 1 to form an emitter diffused region 2. Thereby, as the low-resistance regions 4 are provided in the paths of base lead-out currents 9, the resistance of a base layer is reduced and the switching time of a transistor can be shortened.

公开(公告)号：JPH02114669A

公开(公告)日：1990-04-26

申请号：JP26888188

申请日：1988-10-25

Applicant: SHARP KK

Inventor： YOSHIKAWA TOSHIBUMI ,  KOYAMA JUNICHIRO

IPC: H01L29/74 ,  H01L29/06 ,  H01L29/747

Abstract: PURPOSE:To prevent the occurrence the cracks in a water by a method wherein a mesa type triac is provided with a second layer of a second conductive type which is not only in contact with a mesa groove but also formed on a part of the surface of the second conductivity type first layer, where the second layer is smaller than the second conductivity type first layer in thickness and higher than impurity concentration respectively. CONSTITUTION:When a first conductivity type layer and a second conductivity type layer are formed on an N-type and a P-type semiconductor respectively, a mesa type triac is provided with the following; an N-type substrate 11; a mesa groove 15 formed on both the sides of the substrate 11 and coated with a glass passivation 16; a P -gate diffusion layer 12 formed on the surface of the N-type substrate 11 not in contact with the mesa groove 15; N -diffussion layers 14 formed on a part of the surface of the diffusion layer 12; and a P -compensation diffusion layer 13 which is formed on a part of the surface of the P -gate diffusion layer 12 and whose thickness is larger than that of the P gate diffusion layer 12 and impurity concentration is 2-10 times as high as that of the layer 12. Therefore, the thickness of a wafer remaining after a mesa groove is formed can be made large keeping the wafer excellent in breakdown strength without varying it in a current property or the like and the wafer can be protected from cracks.

公开(公告)号：JPH01315171A

公开(公告)日：1989-12-20

申请号：JP14782288

申请日：1988-06-14

Applicant: SHARP KK

Inventor： KAWANABE HITOSHI ,  KOYAMA JUNICHIRO

IPC: H01L29/74 ,  H01L29/06 ,  H01L29/747

Abstract: PURPOSE:To prevent cracks and chips on glass passivation at the time of dicing by having a PN junction part which is deeply formed at one face side of a substrate and the depth which reaches the PN junction part at the other face side of the board and providing the board with a mesa channel on which the glass passivation is performed. CONSTITUTION:A P -type layer 12 is formed on the lower side surface of an N-type silicon substrate 1 in the form of approximately a mountain, a deep PN junction part 13 is provided, P -type layers 2, 3 are formed on the upper side surface and the lower side surface on the N-type silicon substrate 1, an N -type impurity is diffused on a part of the surface of these P -type layers 2, 3 and N -type layers 4, 5 are formed respectively. Mesa channels 6 which have the depth reaching the PN junction part 13 on the upper side surface of the substrate shaped in this way are formed and the glass passivation 7 is formed on the surface of the mesa channels 6. Finally main electrodes T1, T2 and a gate electrode G are formed and divided into each chip. Thereby cracks and chips on the glass passivation can be prevented from producing at the time of dicing.