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21.发明申请公开(公告)号：US20180351592A1
公开(公告)日：2018-12-06
申请号：US15609337
申请日：2017-05-31
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban
IPC: H04B1/10 , H04B17/318 , H04B17/336 , H03F3/195 , H03G3/00
CPC classification number: H04B1/1036 , H03F3/195 , H03F2200/294 , H03F2200/333 , H03F2200/451 , H03F2200/465 , H03G3/3068 , H03G3/3078
Abstract: In one example, a method includes: at a beginning of a packet communication, setting a maximum gain setting for a plurality of gain components of a receiver; and during a preamble portion of the packet communication, reducing a gain setting for one or more of the plurality of gain components in response to at least one of a first signal output by a first component of the receiver being greater than a first threshold and a second signal output by a second component of the receiver being greater than a second threshold.
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公开(公告)号：US09800281B2
公开(公告)日：2017-10-24
申请号：US15470989
申请日：2017-03-28
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Alessandro Piovaccari , Ramin K. Poorfard , James T. Kao
CPC classification number: H04B1/16 , H03G3/3068
Abstract: A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.
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公开(公告)号：US09748963B2
公开(公告)日：2017-08-29
申请号：US15188272
申请日：2016-06-21
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Mustafa H. Koroglu
CPC classification number: H03M1/002 , H03M1/0626 , H03M1/1009 , H03M1/124 , H03M1/60
Abstract: In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.
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公开(公告)号：US20160380643A1
公开(公告)日：2016-12-29
申请号：US15188272
申请日：2016-06-21
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Mustafa H. Koroglu
CPC classification number: H03M1/002 , H03M1/0626 , H03M1/1009 , H03M1/124 , H03M1/60
Abstract: In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.
Abstract translation: 在一个实施例中，一种装置包括：第一压控振荡器（VCO）模数转换器（ADC）单元，用于接收差分模拟信号的第一部分，并将差分模拟信号的第一部分转换成第一数字 值; 第二VCO ADC单元，用于接收差分模拟信号的第二部分，并将差分模拟信号的第二部分转换为第二数字值; 组合器，用于从第一和第二数字值形成组合的数字信号; 一个抽取电路，用于接收组合的数字信号，并将组合的数字信号滤波成经滤波的组合数字信号; 以及抵消电路，用于至少部分地基于系数值接收经滤波的组合数字信号并产生失真消除的数字信号。
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公开(公告)号：US09106867B2
公开(公告)日：2015-08-11
申请号：US14505701
申请日：2014-10-03
Applicant: Silicon Laboratories Inc.
Inventor： Mustafa H. Koroglu , Abdulkerim L. Coban
IPC: H04N5/50 , H04N5/445 , H04N5/44 , H04N5/455 , H04N21/426 , H04N21/438
CPC classification number: H04N5/4401 , H04N5/455 , H04N5/50 , H04N21/4263 , H04N21/4382
Abstract: An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.
Abstract translation: 一种装置包括用于接收射频（RF）信号并将RF信号提供给调谐器的多个信道的分离器。 每个通道可以包括用于放大RF信号的放大器，使用本地振荡器（LO）信号将放大的RF信号下变频到第二频率信号的混频器，其中每个信道被配置为接收不同的LO信号，滤波器 对下变频的第二频率信号进行滤波，以及数字转换器，对下变频的第二频率信号进行数字化。 时钟发生电路具有多个内插分频器和频率合成器，以产生参考时钟信号。 每个内插分频器被配置为接收参考时钟信号，产生相应的LO信号，并将相应的LO信号提供给至少一个信道的混频器。
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Patent Agency Ranking
26.发明授权公开(公告)号：US08706069B2
公开(公告)日：2014-04-22
申请号：US13923824
申请日：2013-06-21
Applicant: Silicon Laboratories Inc.
Inventor： Ramin Khoini-Poorfard , Alessandro Piovaccari , Aslamali A. Rafi , Mustafa H. Koroglu , David S. Trager , Abdulkerim L. Coban
IPC: H04B1/06
Abstract: A receiver includes an input section, a plurality of RF sections, an output circuit, and a controller. The input section receives and amplifies a radio frequency (RF) input signal to provide an amplified RF signal, and has a gain input. The plurality of RF sections each have an input for receiving the amplified RF signal, and an output for providing an intermediate frequency signal. The output circuit provides an intermediate frequency output signal in response to an output of at least one of the plurality of RF sections. The controller has an output coupled to the gain input of the input section.
Abstract translation: 接收机包括输入部分，多个RF部分，输出电路和控制器。 输入部分接收和放大射频（RF）输入信号以提供放大的RF信号，并具有增益输入。 多个RF部分各自具有用于接收放大的RF信号的输入端和用于提供中频信号的输出端。 输出电路响应于多个RF部分中的至少一个的输出而提供中频输出信号。 控制器具有耦合到输入部分的增益输入的输出。
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27.发明授权公开(公告)号：US10931300B1
公开(公告)日：2021-02-23
申请号：US16588113
申请日：2019-09-30
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Sanjeev Suresh
Abstract: A continuous-time (CT) delta-sigma modulator (DSM) based analog to digital converter (ADC) in a radio receive chain supports a wide range of data rates in a power efficient way in a small die area. The ADC utilizes a 2nd order loop-filter with a single-amplifier loop-filter topology using a two stage Miller amplifier with a feed forward path and a push-pull output stage. High bandwidth operations utilize a “negative-R” compensation scheme at the amplifier input. Negative-R assistance is disabled for low data rate applications. With the negative-R assistance disabled, loop-filter resistor values are increased, instead of only the loop filter capacitor values to scale the noise transfer function (NTF), thereby limiting the capacitor area needed and enabling lower power operation. The NTF zero location is programmable allowing the NTF zero to be located near the intermediate frequency for different bandwidths to reduce the DSM quantization noise contribution for narrow-band (low data rate) applications.
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公开(公告)号：US10826501B1
公开(公告)日：2020-11-03
申请号：US16450083
申请日：2019-06-24
Applicant: Silicon Laboratories Inc.
Inventor： Abdulkerim L. Coban , Wenhuan Yu , Mustafa H. Koroglu
Abstract: A calibration operation adjusts a frequency of a ring oscillator to a desired frequency by adjusting programmable RC circuits in the stages of the ring oscillator. The programmable RC circuits have programmable capacitors, resistors, or both. The RC circuits account for most of the delay through the ring oscillator. Another circuit with its own RC time constant is calibrated based on the adjustments made to the RC circuits in the ring oscillator to achieve the desired frequency.
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公开(公告)号：US10523251B1
公开(公告)日：2019-12-31
申请号：US16156294
申请日：2018-10-10
Applicant: SILICON LABORATORIES INC.
Inventor： Abdulkerim L. Coban , Emmanuel Gautier , Fabrice Portier , Pascal Blouin , Wenhuan Yu
Abstract: A communications receiver with improved blocker performance including multiple gain tables selected based on a number of reductions or back offs from a maximum coarse gain setting. A receiver chain with multiple gain stages converts a received signal to a digital format, determines the power level of the received signal, and provides an overload indication. A first gain table maximizes SNR and SNDR for weak blockers and at least one additional gain table successively improves SNDR for stronger blockers. An AGC circuit initially sets the coarse gain setting to maximum, and backs off a number of coarse gain steps until the receiver chain is not overloaded. The number of back off steps is used to select a gain table, the power level is used to select an entry in the selected table, and the selected entry includes gain settings for the gain stages of the receiver chain.
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公开(公告)号：US09729162B1
公开(公告)日：2017-08-08
申请号：US15223310
申请日：2016-07-29
Applicant: SILICON LABORATORIES INC.
Inventor： Wenhuan Yu , Abdulkerim L. Coban
CPC classification number: H03M1/0617 , H03F3/45183 , H03F3/45475 , H03F3/45636 , H03F3/45659 , H03F2200/267 , H03F2203/45022 , H03F2203/45222 , H03F2203/45418 , H03F2203/45424 , H03F2203/45512 , H03F2203/45526 , H03F2203/45528 , H03F2203/45591 , H03H11/04 , H03H11/0422 , H03H11/1213 , H03K5/1252 , H03M1/00 , H03M1/12 , H03M1/145 , H03M1/502
Abstract: In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.
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