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公开(公告)号：US20240195362A1
公开(公告)日：2024-06-13
申请号：US18063699
申请日：2022-12-09
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi
CPC classification number: H03F1/0288 , H03F1/0227 , H03F3/195 , H03F3/245 , H04B1/0458 , H03F2200/451 , H03F2200/541 , H04B2001/0408
Abstract: In on example, an apparatus includes: a first power amplifier (PA) to receive a first input radio frequency (RF) signal and output a first amplified RF signal; a second PA to receive a second input RF signal and output a second amplified RF signal; and a transformer circuit coupled to an output of the first PA and an output of the second PA. The transformer circuit is to provide, to a load circuit, an RF output signal comprising the first amplified RF signal and the second amplified RF signal.
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2.发明申请公开(公告)号：US20160233919A1
公开(公告)日：2016-08-11
申请号：US15132984
申请日：2016-04-19
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Ravi Kummaraguntla
IPC: H04B1/44 , H03F3/19 , H03F3/21 , H04B1/3805
CPC classification number: H04B1/44 , H03F3/19 , H03F3/211 , H03F3/24 , H03F2200/451 , H03F2203/21103 , H04B1/0458 , H04B1/18 , H04B1/3805 , H04B2001/0408
Abstract: A transceiver includes a transmit/receive terminal, a receiver input terminal, a plurality of impedance transformation networks coupled in series, a plurality of power amplifiers, and a controller. Each impedance transformation network has first and second ports. The impedance transformation networks include at least one selectable impedance transformation network having a resonant mode and a termination mode. The power amplifiers have outputs respectively coupled to the second ports of corresponding ones of the impedance transformation networks. In a receive mode, the controller selects the resonant mode for each selectable impedance transformation network and disables all power amplifiers. In a transmit mode, the controller enables a selected power amplifier and selects the resonant mode of any upstream selectable impedance transformation network, and selects the termination mode of a downstream selectable impedance transformation network.
Abstract translation: 收发器包括发射/接收终端，接收机输入终端，串联耦合的多个阻抗变换网络，多个功率放大器和控制器。 每个阻抗变换网络具有第一和第二端口。 阻抗变换网络包括具有谐振模式和终止模式的至少一个可选择的阻抗变换网络。 功率放大器具有分别耦合到相应的阻抗变换网络的第二端口的输出。 在接收模式下，控制器为每个可选阻抗变换网络选择谐振模式，并禁用所有功率放大器。 在发送模式下，控制器使能所选择的功率放大器，并选择任何上游可选阻抗变换网络的谐振模式，并选择下游可选阻抗变换网络的终端模式。
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3.发明授权Integrated receiver and integrated circuit having integrated inductors and method therefor 有权具有集成电感器的集成接收器和集成电路及其方法公开(公告)号：US09219512B2
公开(公告)日：2015-12-22
申请号：US14612346
申请日：2015-02-03
Applicant: Silicon Laboratories Inc.
Inventor： Ramin Khoini-Poorfard , Alessandro Piovaccari , Aslamali A. Rafi , Mustafa H. Koroglu , David S. Trager , Abdulkerim L. Coban
Abstract: In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.
Abstract translation: 在一种形式中，集成接收器包括跟踪带通滤波器，可调谐低通滤波器和形成在单个集成电路芯片上的混频器。 跟踪带通滤波器具有用于接收射频（RF）输入信号和输出的输入，并且包括与集成电感器并联的具有响应于带通频率控制信号而变化的电容的可变电容器。 集成电感器包括形成在多个金属层中的多个绕组。 可调谐低通滤波器具有耦合到跟踪带通滤波器的输出的输入端和输出端，并具有用于接收截止频率信号的调谐输入端。 混频器具有耦合到可调谐低通滤波器的输出的信号输入，用于接收本地振荡器信号的本地振荡器输入和用于提供经转换的RF信号的信号输出。
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公开(公告)号：US08774750B2
公开(公告)日：2014-07-08
申请号：US13930254
申请日：2013-06-28
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Alessandro Piovaccari
IPC: H04B1/26
CPC classification number: H04B1/16 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D2200/0025 , H03D2200/0084 , H03D2200/0086 , H04N5/455
Abstract: In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.
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公开(公告)号：US20180191384A1
公开(公告)日：2018-07-05
申请号：US15395033
申请日：2016-12-30
Applicant: Silicon Laboratories Inc.
Inventor： Aaron J. Caffee , Brian G. Drost , Alessandro Piovaccari , Aslamali A. Rafi
CPC classification number: H04B1/0475 , H03F1/0205 , H03F1/32 , H03F3/19 , H03F3/21 , H03F2200/451 , H03L7/08 , H04B3/06 , H04B2001/045 , H04L7/0331 , H04L27/364 , H04L27/367
Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09350412B1
公开(公告)日：2016-05-24
申请号：US14558173
申请日：2014-12-02
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Ravi Kummaraguntla
CPC classification number: H04B1/44 , H03F3/19 , H03F3/211 , H03F3/24 , H03F2200/451 , H03F2203/21103 , H04B1/0458 , H04B1/18 , H04B1/3805 , H04B2001/0408
Abstract: A transceiver comprises a transmit/receive terminal, a receiver input terminal, a scalable impedance network, a plurality of power amplifiers, and a receiver. The scalable impedance network is coupled between the transmit/receive terminal and the receiver input terminal and has a plurality of taps in an order between the transmit/receive terminal and the receiver input terminal, in which an impedance looking into any given tap toward the transmit/receive terminal is smaller than an impedance looking into a subsequent tap toward the transmit/receive terminal, if any, in the order. The plurality of power amplifiers are arranged in an order and have outputs respectively coupled to the plurality of taps of the scalable impedance network. A power of any given power amplifier is higher than a power of a subsequent power amplifier, if any, in the order. The receiver is coupled to the receiver input terminal.
Abstract translation: 收发器包括发射/接收终端，接收机输入终端，可伸缩阻抗网络，多个功率放大器和接收机。 可扩展阻抗网络耦合在发射/接收终端和接收机输入终端之间，并且在发射/接收终端与接收机输入终端之间具有多个抽头，其中阻抗将任何给定的抽头看向发射 /接收终端小于按顺序查看朝向发射/接收终端的后续分接头的阻抗（如果有的话）。 多个功率放大器按顺序排列并且具有分别耦合到可伸缩阻抗网络的多个抽头的输出。 任何给定功率放大器的功率高于随后的功率放大器的功率（如果有的话）。 接收器耦合到接收机输入端。
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公开(公告)号：US08880018B2
公开(公告)日：2014-11-04
申请号：US14010993
申请日：2013-08-27
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Alessandro Piovaccari
CPC classification number: H03D7/1466 , H03D7/00 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0086
Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.
Abstract translation: 在一个实施例中，本发明包括一个混频器电路，用于接收和产生来自射频（RF）信号和主时钟信号的混合信号，耦合到混频器电路的输出的开关级，以将混合信号旋转切换到 耦合到开关级的多个增益级，以及组合器，以组合增益级的输出。
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8.发明授权公开(公告)号：US08706069B2
公开(公告)日：2014-04-22
申请号：US13923824
申请日：2013-06-21
Applicant: Silicon Laboratories Inc.
Inventor： Ramin Khoini-Poorfard , Alessandro Piovaccari , Aslamali A. Rafi , Mustafa H. Koroglu , David S. Trager , Abdulkerim L. Coban
IPC: H04B1/06
Abstract: A receiver includes an input section, a plurality of RF sections, an output circuit, and a controller. The input section receives and amplifies a radio frequency (RF) input signal to provide an amplified RF signal, and has a gain input. The plurality of RF sections each have an input for receiving the amplified RF signal, and an output for providing an intermediate frequency signal. The output circuit provides an intermediate frequency output signal in response to an output of at least one of the plurality of RF sections. The controller has an output coupled to the gain input of the input section.
Abstract translation: 接收机包括输入部分，多个RF部分，输出电路和控制器。 输入部分接收和放大射频（RF）输入信号以提供放大的RF信号，并具有增益输入。 多个RF部分各自具有用于接收放大的RF信号的输入端和用于提供中频信号的输出端。 输出电路响应于多个RF部分中的至少一个的输出而提供中频输出信号。 控制器具有耦合到输入部分的增益输入的输出。
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公开(公告)号：US20140038542A1
公开(公告)日：2014-02-06
申请号：US14010993
申请日：2013-08-27
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Alessandro Piovaccari
IPC: H03D7/14
CPC classification number: H03D7/1466 , H03D7/00 , H03D7/1441 , H03D7/1458 , H03D7/1483 , H03D7/165 , H03D2200/0086
Abstract: In one embodiment, the present invention includes a mixer circuit to receive and generate a mixed signal from a radio frequency (RF) signal and a master clock signal, a switch stage coupled to an output of the mixer circuit to rotatingly switch the mixed signal to multiple gain stages coupled to the switch stage, and a combiner to combine an output of the gain stages.
Abstract translation: 在一个实施例中，本发明包括一个混频器电路，用于接收和产生来自射频（RF）信号和主时钟信号的混合信号，耦合到混频器电路的输出的开关级，以将混合信号旋转切换到 耦合到开关级的多个增益级，以及组合器，以组合增益级的输出。
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公开(公告)号：US11038521B1
公开(公告)日：2021-06-15
申请号：US16805336
申请日：2020-02-28
Applicant: Silicon Laboratories Inc.
Inventor： Aslamali A. Rafi , Srisai R. Seethamraju , Russell Croman , James D. Barnette
Abstract: A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.
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