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公开(公告)号：JP2565247B2
公开(公告)日：1996-12-18
申请号：JP12068595
申请日：1995-04-21
Applicant: SONY CORP
Inventor： HAMAZAKI MASAHARU , SUZUKI SATOYUKI , ISHIKAWA KIKUE , YONEMOTO KAZUYA
IPC: H01L27/146 , H04N5/335 , H04N5/341 , H04N5/353 , H04N5/359 , H04N5/369 , H04N5/3728
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公开(公告)号：JPH0846875A
公开(公告)日：1996-02-16
申请号：JP12068595
申请日：1995-04-21
Applicant: SONY CORP
Inventor： HAMAZAKI MASAHARU , SUZUKI SATOYUKI , ISHIKAWA KIKUE , YONEMOTO KAZUYA
IPC: H01L27/146 , H04N5/335 , H04N5/341 , H04N5/353 , H04N5/359 , H04N5/369 , H04N5/3728
Abstract: PURPOSE:To variably and satisfactorily control exposure time at desired time by applying electrical control and to reduce power conssumption. CONSTITUTION:This solid-state image pickup device provided with a first conductive semiconductor substrate 1, a second conductive area 2 formed on the first conductive semiconductor substrate 1 and a signal charge accumulation area 3 formed on the surface of the second conductive area 2 and in which a sweep voltage is supplied to the first conductive semiconductor substrate 1 and a signal charge accumulated in the signal charge accumulation area 3 can be swept to the first conductive semiconductor substrate 1 is constituted in such a way that the sweep voltage to be supplied to the first conductive semiconductor substrate 1 is formed in pulsative shape, and the exposure time can be controlled by varying a time to supply such pulsative sweep voltage.
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公开(公告)号：JPS6315459A
公开(公告)日：1988-01-22
申请号：JP15928186
申请日：1986-07-07
Applicant: SONY CORP
Inventor： YONEMOTO KAZUYA , HAMAZAKI MASAHARU , KAGAWA TAKAAKI , SUZUKI SATOYUKI , ISHIKAWA KIKUE
IPC: H01L27/148 , H04N5/335 , H04N5/341 , H04N5/3728
Abstract: PURPOSE:To improve the efficiency of transfer of charges, by varying a channel width or an insulating film thickness in the direction of transfer in each transfer electrode so as to generate an electric field in the direction of transfer. CONSTITUTION:A vertical transfer register 2 is so formed that a channel region 4 has a small width W1 in the front half part in the direction of transfer and a large width W2 in the rear half part in said direction so that a channel width be varied toward the direction of transfer in each transfer electrode 5, i.e., in each transfer element 8. According to this construction, a potential difference is produced between the front half and rear half parts different in the channel width from each other, and thereby a fringing electric field in the direction of transfer is intensified. Therefore charge transfer in each transfer element 8 is improved, and the transfer efficiency of the vertical transfer register 2 in the case when a channel is narrowed as a whole can be increased.
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公开(公告)号：JPH10145683A
公开(公告)日：1998-05-29
申请号：JP29303296
申请日：1996-11-05
Applicant: SONY CORP
Inventor： BITO KENJI , FUKUI HIROSHI , ISHIKAWA KIKUE
Abstract: PROBLEM TO BE SOLVED: To enable the setting operation of shutter speed even in a single use state by providing a signal select switch for selecting either an external shutter control signal or a shutter control signal supplied from a trigger shutter control part. SOLUTION: A signal selection switch 7 is an analog switch for selectively supplying either the external shutter control signal inputted through a shutter control signal input terminal 13 or the shutter control signal supplied from a trigger shutter control part 5 to a CCD driving part 2. While the switch control signal supplied from an external connecting state discriminating part 8 is at a high level, the shutter control signal from the trigger shutter control part 5 is supplied to the CCD driving part 2 and while the switch control signal is at a low level, the external shutter control signal from the shutter control signal input terminal 13 is supplied to the CCD driving part 2. Corresponding to the external connecting state of the shutter control signal input terminal 13, the signal selection switch can be automatically switched and controlled as well.
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公开(公告)号：JPH08241978A
公开(公告)日：1996-09-17
申请号：JP5352096
申请日：1996-03-11
Applicant: SONY CORP
Inventor： YONEMOTO KAZUYA , HAMAZAKI MASAHARU , KAGAWA TAKAAKI , SUZUKI SATOYUKI , ISHIKAWA KIKUE
IPC: H01L27/148 , H04N5/335 , H04N5/341 , H04N5/369 , H04N5/3728
Abstract: PURPOSE: To improve the charge transfer efficiency of a vertical transfer register and to suppress a chip size in an interline-type CCD solid-state imaging device. CONSTITUTION: An interline-type CCD solid-state imaging device is provided with a plurality of light-receiving parts 1 which are arranged in the horizontal direction and the vertical direction and with a vertical transfer register 2 which is arranged via a read gate part 7 on one side part of the light-receiving parts 1. In the interline-type CCD solid-state imaging device, the vertical transfer register 2 is composed of a channel region 4 and of a plurality of transfer electrodes 5 formed on the channel region 4 via an insulating film. The read gate part 7 is formed so as to come into contact with at least the central part of a substantial region which contributes toward the channel formation of the respective transfer electrodes 5, and the channel width of the channel region 4 which is situated inside the respective transfer electrodes and which comes into contact with the read gate part 7 is expanded sequentially in a transfer direction at one stage or so as to be divided into a plurality of stages.
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Patent Agency Ranking
公开(公告)号：JPH05153502A
公开(公告)日：1993-06-18
申请号：JP31253691
申请日：1991-11-27
Applicant: SONY CORP
Inventor： ISHIKAWA KIKUE
Abstract: PURPOSE:To reduce the power consumption by applying a signal whose frequency is lower than that of a line shift pulse to an image section for a period after a charge stored in the image section is read out till it is swept out. CONSTITUTION:A line shift pulse outputted from a line shift timing generator 19 is fed to a storage section driver 22, in which the pulse is subject to line shift and the result is fed to a 1/n frequency divider 24. The frequency divider 24 frequency-divides the line shift pulse by a prescribed frequency division ratio and the result is fed to a synthesis display circuit 20. The circuit 20 synthesizes a sweepout pulse outputted from a sweepout timing generator 17, a frame shift pulse outputted from a frame shift timing generator 18 and a pulse outputted from the frequency divider 24 into one system of an output. Then the result is fed to an image section 2 via a driver 21 of the image section together with a read timing pulse. Thus, an output of the frequency divider 24 is fed to the image section 2 for a period from read to sweepout and the power consumption is reduced.
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公开(公告)号：JPH0434977A
公开(公告)日：1992-02-05
申请号：JP13963390
申请日：1990-05-31
Applicant: SONY CORP
Inventor： ISHIKAWA KIKUE , ARAI YASUAKI
Abstract: PURPOSE:To notably lower the flare level by focusing an incident light on a reflection preventive film in an optical black part. CONSTITUTION:A beam of light Po supposed to enter through the intermediary of a seal glass 7 enters in a focusing lenses 6 on an optical black part (OPB). The beam of light Po is reflected at the interface of the focusing lenses 6 to advance toward a dyeing layer 5. Since this dyeing layer 5 functions as a reflection preventive film, the reflected light P1 is dimmed with the dyeing layer 5 so that the intensity of the reflected light P2 from the dyeing layer 5 may satisfactorily be decreased. Accordingly, the reflection of the light focused on the focusing lenses 6 can be avoided thereby enabling the flare level to be satisfactorily lowered.
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公开(公告)号：JPS63105579A
公开(公告)日：1988-05-10
申请号：JP25237586
申请日：1986-10-23
Applicant: SONY CORP
Inventor： YONEMOTO KAZUYA , KAGAWA TAKAAKI , ISHIKAWA KIKUE , SUZUKI SATOYUKI , HAMAZAKI MASAHARU
IPC: H01L27/148 , H01L27/14 , H04N5/335 , H04N5/341 , H04N5/353 , H04N5/359 , H04N5/369 , H04N5/3728
Abstract: PURPOSE:To obtain a reproducing image with uniform contrast, by constituting a device so that a prescribed voltage is impressed on a conductive type semiconductor substrate in a horizontal blanking period. CONSTITUTION:A voltage VH, for example, 30(V) is impressed on an N-type silicon substrate 4 in the horizontal blanking period, and signal charge accumulated in a signal charge accumulating area 6 is swept to the N-type silicon substrate 4. In other words, the voltage 30V is impressed on the N-type silicon substrate 4 at every horizontal blanking period until just before exposure is started after reading by a read pulse P1, and the signal charge accumulated in the signal charge accumulating area 6 is swept, and in an exposure time=t2, the signal charge is accumulated by setting the voltage at 10V to be impressed on the N-type silicon substrate 4. Thus, since the period where the voltage VH, for example, 30V is impressed on the N-type silicon substrate 4 is set in the horizontal blanking period, no influence is given on the reproducing image even when the buffer amplifier of an output part, etc., receives modulation due to the varying of the voltage impressed on the N-type silicon substrate, and the reproducing image with the uniform contrast can be obtained.
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公开(公告)号：JPS6336562A
公开(公告)日：1988-02-17
申请号：JP18040486
申请日：1986-07-31
Applicant: SONY CORP
Inventor： KAGAWA TAKAAKI , ISHIKAWA KIKUE , SUZUKI SATOYUKI , HAMAZAKI MASAHARU , YONEMOTO KAZUYA
IPC: H01L21/339 , H01L27/148 , H01L29/762 , H04N5/335 , H04N5/341 , H04N5/369 , H04N5/372 , H04N5/374
Abstract: PURPOSE:To avoid the yield of delay due to the presence of resistance in a gate electrode effectively, by forming the gate electrode of an MOS transistor at least at a final stage in an output means by using electrodes constituting a charge transfer means and at least two layers, which are selected among light screening conductor films and interconnections. CONSTITUTION:On a semiconductor substrate 1, an image sensing means, a charge transfer means 3 and an output means are provided. A lightscreening conductor film 5, in which a light receiving hole part is provided, is formed on the arranging part of the image sensing means. In this solid-state image sensing device, a gate electrode 12 of an MOS transistor at least at a final stage in the output means 4 has the following laminated structure. A lower electrode layer 12A is formed by the same process for a first transfer electrode 8 constituting the charge transfer means 3. An upper electrode layer 12B is formed by other electrodes, e.g., a second transfer electrode 9 and electrodes 13 and 14, and other conducting films such as the light-screening conductor film 5, interconnections or the like. The electrode 12 is formed by the electrode layers 12A and 12B. Then, e.g., the lower electrode layer 12A and the upper electrode layers 12B are electrically connected at both ends.
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公开(公告)号：JPS62277863A
公开(公告)日：1987-12-02
申请号：JP12068886
申请日：1986-05-26
Applicant: SONY CORP
Inventor： YONEMOTO KAZUYA , HAMAZAKI MASAHARU , KAGAWA TAKAAKI , ISHIKAWA KIKUE , SUZUKI SATOYUKI
IPC: H01L27/148 , H01L27/14 , H04N5/335 , H04N5/341 , H04N5/347 , H04N5/351 , H04N5/357 , H04N5/3728
Abstract: PURPOSE:To eliminate the so-called flicker of a reproduced picture by using a same waveform of a clock pulse before the read pulse signal of a 4-phase clock pulse signal for an even order field and an odd order field. CONSTITUTION:The clock pulse signal waveform before read pulse signals POA, POC of 4-phase clock pulse signals phiOA-phiODis made the same for an even number order field and an odd number order field. Even if a part of a signal electric charge remains in the electronic charge storage region 6 of a photoelectric conversion section 3, the depth of potential of the electric charge storage area 6 of the photoelectric conversion section 3 is made coincident for the even number field read and the odd number field read, and since the signal charge remaining in the charge storage region 6 at read is the same for the enven number field read and the odd number field read, no flicker is caused in the reproduced picture.
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