公开(公告)号：JPH1064984A

公开(公告)日：1998-03-06

申请号：JP21622696

申请日：1996-08-16

Applicant: SONY CORP ,  SOZO KAGAKU KK

Inventor： KADOMURA SHINGO ,  SHIROSAKI TOMOHIDE ,  HIRANO SHINSUKE ,  MIYASHITA KINYA ,  TATSUMI YOSHIAKI ,  MIYATA SEIICHIRO

IPC: H01L21/302 ,  H01L21/205 ,  H01L21/3065 ,  H01L21/68 ,  H01L21/683

Abstract: PROBLEM TO BE SOLVED: To provide the wafer stage by which plasma processing is attained under a condition of high temperature heating by establishing an electrostatic chuck technology whose temperature control performance is especially improved. SOLUTION: The wafer stage 1 is made up of an electrostatic chuck 3 and a temperature adjustment jacket 2 placed under the electrostatic chuck 3. The electrostatic chuck 3 is provided with a dielectric body 4 made of an insulating material, an electrode 5 consisting of a soldered layer placed to a lower side of the dielectric body 4 to fix the dielectric body 4, an aluminum nitride plate 6 placed to a lower side of the electrode 5 to fix the dielectric body 4 with the electrode 5, a heater 7 placed to a lower side of the aluminum nitride plate 6 to heat the dielectric body 4 and a metallic plate 8b placed to the lower side of the aluminum nitride plate 6 and placed to an upper side or a lower side of the heater 7. The temperature adjustment jacket 2 is provided with a temperature adjustment means.

公开(公告)号：JPH1064983A

公开(公告)日：1998-03-06

申请号：JP21622596

申请日：1996-08-16

Applicant: SONY CORP ,  SOZO KAGAKU KK

Inventor： KADOMURA SHINGO ,  SHIROSAKI TOMOHIDE ,  HIRANO SHINSUKE ,  MIYASHITA KINYA ,  TATSUMI YOSHIAKI ,  MIYATA SEIICHIRO

IPC: C23C16/44 ,  C23C16/14 ,  C23C16/34 ,  C23C16/40 ,  C23C16/458 ,  H01L21/00 ,  H01L21/683 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To provide the wafer stage by which plasma processing is attained under a condition of high temperature heating, especially under a condition at a temperature of 400 deg.C or over by establishing an electrostatic chuck technology whose temperature control performance is improved. SOLUTION: The wafer stage 1 is made up of an electrostatic chuck 3 and a temperature adjustment jacket 2 placed under the electrostatic chuck 3. The electrostatic chuck 3 is provided with a dielectric body 4 made of an insulating material, an electrode 5 consisting of a soldered layer placed to a lower side of the dielectric body 4, an aluminum nitride plate 6 placed to a lower side of the electrode 5, a heater 7 placed to a lower side of the aluminum nitride plate 6 and a metallic plate 8b placed to the lower side of the aluminum nitride plate 6 and placed to an upper side or a lower side of the heater 7. The temperature adjustment jacket 2 is made of a composite aluminum material made by complexing inorganic fibers and an aluminum or an aluminum alloy under a high pressure and provided with a temperature adjustment means.

公开(公告)号：JPH1027786A

公开(公告)日：1998-01-27

申请号：JP7896797

申请日：1997-03-13

Applicant: SONY CORP

Inventor： KADOMURA SHINGO

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device wherein trenches of high aspect ratio such as holes, channels are controlled into good shape and formed efficiently with high etching rate in a method for manufacturing semiconductor devices by a process of trench etching for silicon. SOLUTION: In a method for manufacturing semiconductor devices by a process of trench etching for a silicon substrate 1, gas containing silicon chloride, nitrogen and chlorine such as mixing gas of SiCl4 , N2 , and Cl2 is used as etching gas. Plasma etching is performed to form a trench 2 while silicon nitride 3 is deposited on silicon side wall of the trench 2 formed during the etching.

公开(公告)号：JPH09298192A

公开(公告)日：1997-11-18

申请号：JP4316997

申请日：1997-02-27

Applicant: SONY CORP

Inventor： KADOMURA SHINGO

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/68 ,  H01L21/683 ,  H02N13/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing apparatus by which a low temperature etching technology is really made to fit for practical use. SOLUTION: A semiconductor device manufacturing apparatus has a vacuum chamber 2 in which a sample stage 12 equipped with a cooling means is provided and a plasma generating means which generates a plasma. A semiconductor substrate W placed on the sample stage 12 is treated by the generation of the plasma while the cooling means cools the sample stage 12 to control the temperature of the sample stage 12. Liquefied gas or air is used as the coolant of the cooling means. As the flow routs of the coolant, a plurality of pipes having different diameters are provided in parallel with each other at positions before the coolant flows into the sample stage 12. The coolant is supplied to the sample stage 12 through the pipes to cool the stage 12. An control means which controls the respective quantities of the coolant supplied to a plurality of the pipes is provided in the cooling means.

公开(公告)号：JPH09260474A

公开(公告)日：1997-10-03

申请号：JP6562596

申请日：1996-03-22

Applicant: SONY CORP ,  SOZO KAGAKU KK

Inventor： KADOMURA SHINGO ,  SHIROSAKI TOMOHIDE ,  HIRANO SHINSUKE ,  MIYASHITA KINYA ,  MIYATA SEIICHIRO ,  TATSUMI YOSHIAKI

IPC: B23Q3/15 ,  H01L21/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/683 ,  H02N13/00 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To change the temperature of a wafer in short time without affecting throughput by providing a dielectric made of an insulating material, an electrode made of a conductor below the dielectric and a heater for heating the dielectric below the electrode. SOLUTION: The electrostatic chuck 3 is constituted of the dielectric 4 made of the insulating material, the electrode 5 made of the conductor provided on the lower face of the dielectric and the heater 6 provided below the electrode 5. An insulating body 7 which is almost columnar is provided between the electrode 5 and the heater 6. The dielectric 4 is made of the insulating material of high heat conductivity and the material of the electrode 5 is not especially restricted if it is made of the conductor of metal or alloy. The heater 6 is formed by alloy constituted of Fe, Cr and Al, for example. Thus, heat by means of heating by heater 6 is speedily transmitted to the dielectric through the electrode 5, and switching from a low temperature to a high temperature can be executed in short time.

公开(公告)号：JPH09186069A

公开(公告)日：1997-07-15

申请号：JP83696

申请日：1996-01-08

Applicant: SONY CORP

Inventor： KADOMURA SHINGO

IPC: G03F7/11 ,  G03F7/26 ,  H01L21/027

Abstract: PROBLEM TO BE SOLVED: To prevent the occurrence of side etching or pattern conversion difference by constituting with a material containing fluorine for at least one kind among a lower organic flattening layer pattern and an intermediate layer pattern. SOLUTION: A lower organic flattening layer 5 comprising fluorine-based polymer, an intermediate layer 6 and an upper resist layer 7 are the basic configuration for a resist pattern. A CF-based reaction product of a low molecular weight released by the etching of the lower organic flattening layer 5 is re-polymerized and re-stuck on a side wall of the pattern of the lower organic flattening layer 5 being etched. And the etching progresses while forming a strong side wall protection film 8. As a result, side etching or pattern conversion difference does not occur on the pattern of the lower organic flattening layer 5.

公开(公告)号：JPH09172053A

公开(公告)日：1997-06-30

申请号：JP1977296

申请日：1996-02-06

Applicant: SONY CORP

Inventor： HIRANO SHINSUKE ,  SHIROSAKI TOMOHIDE ,  HATTORI TADASHI ,  KADOMURA SHINGO

IPC: C23C16/50 ,  C23C16/52 ,  H01L21/203 ,  H01L21/205 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/68 ,  H01L21/683

Abstract: PROBLEM TO BE SOLVED: To control the temperature of a semiconductor substrate with high precision, during plasma-processing the semiconductor substrate. SOLUTION: A semiconductor substrate W is put on a sample stage 3 provided with a cooling means 9 and a heating means 8, and the semiconductor substrate W is processed by generating a plasma P, adjusting the temperature of the sample stage 3 by the cooling means 9 and the heating means 8 and adjusting the temperature of the semiconductor substrate W. The degree of heating by the heating means 8 is lowered by an amount set beforehand when the plasma P is generated, and the degree of heating is returned to its original value at the end of the generation of the plasma P.

公开(公告)号：JPH09153483A

公开(公告)日：1997-06-10

申请号：JP31335695

申请日：1995-11-30

Applicant: SONY CORP

Inventor： KADOMURA SHINGO

IPC: H01L21/302 ,  H01L21/027 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To protect an organic low-dielectric film against corrosion when an organic resist pattern is ashed on an interlayer insulating film which includes the organic low-dielectric film. SOLUTION: An organic low-dielectric film 3 is higher in weight change point on thermogravimetric analysis and glass transition point, than a usual organic resist material, so that resist ashing is carried out cooling down a substrate 1 up to a room temperature and taking advantage of a heat resistant property difference between the film 3 and resist. By this setup, even if an organic resist pattern serving as an etching mask is ashed after a connection opening is bored in an interlayer insulating film 5 of three-layered structure composed of a lower SiOx film 2, the organic low-dielectric film 3, and an upper SiOx film 4, the organic low-dielectric film 3 is prevented from being corroded through its processed surface, the connection hole 7 is can be kept anisotropic in shape. A reduction in ashing rate due to cooling of the substrate can be compensated by a combination of plasma of high density and a substrate bias.

公开(公告)号：JPH0869896A

公开(公告)日：1996-03-12

申请号：JP20564594

申请日：1994-08-30

Applicant: SONY CORP

Inventor： KADOMURA SHINGO

IPC: H05H1/46 ,  C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/31

Abstract: PURPOSE: To provide an asking method, having high throughput, cleanness, and low damage, for a resist mask having a decomposition hardening layer by high-dose ion injection. CONSTITUTION: A decomposition hardening layer 3 increases an ion mode by high-density plasma by helicon wave plasma, and performs asking at low temperature to prevent popping. Then an inner peripheral solenoid coil contributing to the transmission of a helicon wave is cut to switching to an inductive coupling plasma mode, and radicalness is increased to ask an unaltered part 2. As a result, the ion mode and a radical mode can be treated to eliminate lowering throughput following carrying a base board to be treated by one high-density plasma treatment device. The joint use of base board heating by a halogen lamp can realize faster treatment.

公开(公告)号：JPH07297281A

公开(公告)日：1995-11-10

申请号：JP10769294

申请日：1994-04-22

Applicant: SONY CORP

Inventor： AKIBA NAMISATO ,  KADOMURA SHINGO

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522

Abstract: PURPOSE:To improve coverage when forming a film and to enhance yield of a multilayer wiring process by preventing a re-deposit from being adhering the side wall of a hole when forming a connection hole leading to a lower-layer wiring at an insulation film by etching. CONSTITUTION:After forming a wiring film 12 consisting of aluminum metal, an etching stop film 13 consisting of titanium nitride or titanium nitride oxide by a substance succeeding to the orientation of aluminum metal and having (111) orientation is formed without exposing the surface to oxidation atmosphere and further a reflection prevention film 14 is formed. Then, those films are subjected to patterning and a wire 15 is formed. Then, after an insulation film 16 is formed to a state for covering the wiring 15, a connection hole 19 is formed at the insulation film 16 on the wiring 15.