PROCESSOR AND METHOD FOR IMAGE PROCESSING

    公开(公告)号:JPH10134175A

    公开(公告)日:1998-05-22

    申请号:JP28657196

    申请日:1996-10-29

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To enlarge or reduce an image at an arbitrary conversion rate. SOLUTION: A residue circuit 11 outputs a phase variation component Pd supplied from a specific device and the decimal part of the sum of the value of a register 12 to the register 12. An approximation circuit 13 outputs a filter select signal Pi whose phase (x) corresponds to a filter coefficient set corresponding to the phase closest to the value of the register 12 to a coefficient memory 1A. Thus, an optimum filter coefficient set among a specific number of filter coefficient sets is selected for the interpolation of specific pixel data. Then product sum operations between the four filter coefficient sets and four pixel data are performed by multipliers 3-1 to 3-4 and an adder by a Cubic approximating method to calculate an interpolated value of pixels.

    IMAGE PROCESSOR AND METHOD THEREFOR

    公开(公告)号:JPH10124656A

    公开(公告)日:1998-05-15

    申请号:JP27599696

    申请日:1996-10-18

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To operate the processing of an image by a processor in an SIMD (single instruction multiple data stream) form. SOLUTION: Input data for one pixel are supplied to each element processor 31. Data supplied to the prescribed element processor 31 is defined as R0 , and data supplied to the element processors 31 which are left-hand, left-hand next to it, right-hand, right-hand next to is, and right-hand next to it are respectively defined as R-1 , R-2 , R+1 , R+2 , and R+3 . The element processor 31 uses a preliminarily supplied filter coefficient set (FC1, FC2, FC3, and FC4), and outputs R-1 ×FC1+R0 ×FC2+R+2 ×FC3+R+3 ×FC4 or R-2 ×FC1+R0 ×FC2+R+1 ×FC3+ R+2 ×FC4 as output data according to the position relation of the pixels corresponding to the output data.

    PARALLEL PROCESSOR
    23.
    发明专利

    公开(公告)号:JPH08123769A

    公开(公告)日:1996-05-17

    申请号:JP7581195

    申请日:1995-03-31

    Applicant: SONY CORP

    Abstract: PURPOSE: To provide a parallel processor capable of reducing the redundancy of circuit constitution of processor elements without reducing the performance of the processor elements and capable of reducing circuit size and power consumption. CONSTITUTION: The parallel processor 1 converts the picture element value Di of a video signal for one horizontal period serially and successively inputted from an input data terminal in horizontal periods Hk (k=1, 2,...) e.g. into parallel data by an input shift register 12, supplies the parallel data to respective memory circuits 104i and arithmetic circuits 106i in a horizontal blanking period Bk following the horizontal period Hk , applies prescribed processing to the picture element value Di by the circuits 106i in a following horizontal period Hk+1 , supplies arithmetic processing results Qi to an output shift register 14 in a following blanking period Bk+1 , and then successively and serially outputs the results Qi from an output data terminal in a following horizontal period Hk+2 .

    IMAGE SIGNAL PROCESSOR
    24.
    发明专利

    公开(公告)号:JPH07210662A

    公开(公告)日:1995-08-11

    申请号:JP131194

    申请日:1994-01-11

    Applicant: SONY CORP

    Abstract: PURPOSE:To perform the parallel processing of picture element data in every one horizontal period even in the case of an image signal having a short horizontal blanking period. CONSTITUTION:Picture element data is inputted from an input terminal in the horizontal period and is held in an input buffer 120 for a prescribed time and is transferred to a shift register 130 after reserving a prescribed blanking period. This input picture element data is transferred from the shift register 130 to operation parts 151 to 153 in the next blanking period, and the operation processing is performed in the next horizontal period. After transfer of input picture element data in the next blanking period, data of the operation result is transferred to the shift register 130. In the next horizontal period, the result data is transferred to an output buffer 140 simultaneously with transfer of input picture element data. The output buffer 140 holds the result data and outputs this data synchronously with a desired output signal by reduction of the blanking period or the like.

    PROCESSING CIRCUIT FOR DISPLAY DATA

    公开(公告)号:JPH03249793A

    公开(公告)日:1991-11-07

    申请号:JP4863890

    申请日:1990-02-28

    Applicant: SONY CORP

    Abstract: PURPOSE:To execute the fault diagnosis of a memory, etc., and the detection of a fault part by a host computer by providing a control part for generating a load signal to a register by a request from the host computer. CONSTITUTION:A host computer, first of all, sets an image memory and a look-up table 21. In a specific address of the image memory, an address of the look-up table 21 to be tested is written, and its address is written in an address register 12. On the other hand, to the address of the designated look-up table 21, a known RGB code is set, and to addresses of the image memory and the look-up table 21 except said address, other code is set. In a blanking period, a load signal is supplied to a register 25, and output data supplied to a D/A converter is inputted. This contents are read out by the host computer and whether the set RGB code is obtained or not is decided. In such a way, a fault part can be detected easily.

    PROCESSING CIRCUIT FOR DISPLAY DATA

    公开(公告)号:JPH03249792A

    公开(公告)日:1991-11-07

    申请号:JP4863790

    申请日:1990-02-28

    Applicant: SONY CORP

    Abstract: PURPOSE:To execute the fault diagnosis of a memory, etc., and the detection of a fault part by a host computer by providing a control part for generating a load signal to a register by a request from the host computer. CONSTITUTION:A host computer, first of all, sets an image memory and a look-up table 21 to a color to be tested. The image memory is painted out in this color, and all pixels of the image memory are set so as to designate a specific address of the look-up table 21. To the specific address of the look-up table 21, an RGB code of a color to be tested is set, and to other address than said address, other code is set. In such a state, in a blanking period, a load signal is supplied to a register 25, and the register 25 inputs output data supplied to a D/A converter. By reading out the contents of this register 25 by the host computer, whether the set RGB code is obtained or not is decided. In such a way, a fault part can be detected easily.

    Display device and display control method
    27.
    发明专利
    Display device and display control method 有权
    显示设备和显示控制方法

    公开(公告)号:JP2013205526A

    公开(公告)日:2013-10-07

    申请号:JP2012072669

    申请日:2012-03-28

    Abstract: PROBLEM TO BE SOLVED: To improve convenience of a display device constituted by using a transparent display.SOLUTION: A display device includes a transparent display, a sensor unit for obtaining peripheral information of the transparent display, and a control unit for controlling the display state of the transparent display on the basis of the output of the sensor unit. For example, the display state of the transparent display is controlled so as to remove foreign matters from an image observed through the transparent display to improve an ambient property. Also, for example, the display state of the transparent display is controlled so that it is difficult for external people to understand the display content of the transparent display, and thereby attaining privacy protection.

    Abstract translation: 要解决的问题:提高由使用透明显示器构成的显示装置的便利性。显示装置包括透明显示器,用于获得透明显示器的周边信息的传感器单元和用于控制显示状态的控制单元 基于传感器单元的输出的透明显示。 例如,透明显示器的显示状态被控制,以便通过透明显示器观察到的图像中的异物去除以改善环境特性。 此外,例如,透明显示器的显示状态被控制,使得外部用户难以理解透明显示器的显示内容,从而实现隐私保护。

    Image processing device and method, and program
    28.
    发明专利
    Image processing device and method, and program 有权
    图像处理设备及方法及程序

    公开(公告)号:JP2009038620A

    公开(公告)日:2009-02-19

    申请号:JP2007201593

    申请日:2007-08-02

    Abstract: PROBLEM TO BE SOLVED: To generate an image of an interpolating frame with higher accuracy.
    SOLUTION: A motion compensating part 23 and a motion compensating part 24 perform motion compensation by using input images of temporally previous and following frames of an interpolating frame to generate a previous interpolating image and a following interpolating image. An image generating part 25 outputs the pixel of the previous interpolating image of the same position as a pixel under consideration when the previous reference pixel of the input image of the previous frame obtained by moving the pixel under consideration only for the motion of a motion vector is within an effective region and also when the following reference pixel of the input image of the following frame obtained by moving the pixel under consideration only for the motion of the motion vector is not within the effective region by sequentially defining the pixel of an interpolating image of an interpolating frame to be generated from now on as the pixel under consideration, and outputs the pixel of the following interpolating image of the same position as the pixel under consideration as a pixel under consideration when the previous reference pixel is not within the effective region and also when the following reference pixel is within the effective region. This invention is applicable to an image processing device.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题:以更高的精度产生内插帧的图像。 解决方案:运动补偿部分23和运动补偿部分24通过使用内插帧的时间上先前和后续帧的输入图像来执行运动补偿,以产生先前的内插图像和随后的内插图像。 当通过仅考虑运动矢量的运动来移动所考虑的像素而获得的前一帧的输入图像的先前参考像素时,图像生成部分25输出与所考虑的像素相同位置的先前内插图像的像素 在有效区域内,并且当通过仅针对运动矢量的运动移动仅考虑运动的像素而获得的后续帧的输入图像的后续参考像素不在有效区域内时,通过依次定义内插图像的像素 从现在开始产生的内插帧作为所考虑的像素,并且当先前的参考像素不在有效区域内时,将与所考虑的像素相同位置的下一个内插图像的像素作为所考虑的像素输出 并且当以下参考像素在有效区域内时也是如此。 本发明可应用于图像处理装置。 版权所有(C)2009,JPO&INPIT

    Signal processing device, method, and program
    29.
    发明专利
    Signal processing device, method, and program 审中-公开
    信号处理设备,方法和程序

    公开(公告)号:JP2006042300A

    公开(公告)日:2006-02-09

    申请号:JP2004326406

    申请日:2004-11-10

    Abstract: PROBLEM TO BE SOLVED: To individually execute a plurality of different signal processings using predetermined kinds of control signals. SOLUTION: A main signal propagating part 263 propagates a main signal from a signal input part 261 to a signal output part 265, by sequentially executing N signal processings using the control signals for the main signal input to the signal input part 261. A control signal generating part 262 generates control signals in the form corresponding to the signal processing executed by a first signal processing part 263-1 of the main signal propagating part 263, and supplies them to the first signal processing part 263-1. When processings are sequentially executed by a second signal processing part 263-2 or an N signal processing part 263-N of the main signal propagating part 263, respectively, a control signal propagating part 264 sequentially converts the control signals generated by the control signal generating part 262 into the forms corresponding to signal processing to be executed by the main signal propagating part 263, and sequentially supplies them to the main signal propagating part 263. This device is applicable to a television system. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题:使用预定种类的控制信号分别执行多个不同的信号处理。 解决方案:主信号传播部分263通过使用输入到信号输入部分261的主信号的控制信号依次执行N信号处理,将主信号从信号输入部分261传播到信号输出部分265。 控制信号生成部262以与主信号传播部263的第一信号处理部263-1执行的信号处理对应的形式生成控制信号,并将其提供给第一信号处理部263-1。 当分别由主信号传播部分263的第二信号处理部分263-2或N信号处理部分263-N依次执行处理时,控制信号传播部分264依次转换由产生的控制信号产生的控制信号 部分262形成与由主信号传播部分263执行的信号处理相对应的形式,并且将它们顺序地提供给主信号传播部分263.该装置可应用于电视系统。 版权所有(C)2006,JPO&NCIPI

    DATA OPERATION UNIT, ITS METHOD AND TRANSMISSION MEDIUM

    公开(公告)号:JPH1153171A

    公开(公告)日:1999-02-26

    申请号:JP21025697

    申请日:1997-08-05

    Applicant: SONY CORP

    Abstract: PROBLEM TO BE SOLVED: To reduce steps of a program. SOLUTION: Bit length of an operand with longer bit length among a first operand or a second operand is loaded on a repeat counter 52, the bit length of an operand with shorter bit length is loaded on a bit counter 53 and the operands are decreased as well as a repeat processing by a sequencer 50. Repetition frequency of the repeat processing is set as the counted number of the repeat counter plus one. After a value of the bit counter 53 becomes zero, when the operand with shorter bit length is a complement of two, its MSB is supplied to a full adder and when the operand is a straight binary number, a value zero is supplied to the full adder. In addition, in the last clock of the repeat processing by the sequencer 50, the operand with longer bit length is the complement of two, its MSB is supplied to the full adder and when the operand is the straight binary number, the value zero is supplied to the full adder.

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