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公开(公告)号：DE69131938T2
公开(公告)日：2000-06-15
申请号：DE69131938
申请日：1991-11-29
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO
IPC: H04N11/04 , G06T7/20 , G06T9/00 , H04N1/41 , H04N1/415 , H04N5/14 , H04N19/119 , H04N19/139 , H04N19/176 , H04N19/196 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/503 , H04N19/51 , H04N19/60 , H04N19/61 , H04N19/625 , H04N7/30 , H04N7/50
Abstract: A motion vector detection apparatus comprises a delay circuit for receiving first picture data and for outputting a particular detection range of picture data, a block comparison circuit for receiving both second picture data with a particular time difference from the first picture data and picture data from the delay circuit and for detecting a difference between picture data from the delay circuit and second picture data for each block of P x Q picture elements, and a determination circuit for determining a degree of matching of a picture of an output signal from the block comparison circuit. The delay circuit comprises a scanning conversion circuit for converting input picture data from conventional horizontal scanning into scanning within the block, and a number of shift registers for receiving the first picture data with a delay of one frame. The shift registers are arranged such that both a first block of P x Q picture elements which are earlier than a particular reference tap of the shift registers and a second block which deviates by i picture elements horizontally and by j picture elements vertically from the first block are set, and such that when the first block does not deviate from the second block, a tap with a delay which is equal to the difference between each picture element of the second block and the reference tap is selected, the second picture data being obtained from the selected tap.
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公开(公告)号：FR2529425B1
公开(公告)日：1987-07-10
申请号：FR8310693
申请日：1983-06-28
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO , ASAIDA TAKASHI , NAGUMO FUMIO
Abstract: A digital encoder for use with digital luminance and chrominance signals having black levels includes a level adjusting circuit which adjusts the chrominance and luminance signals to establish a predetermined relationship between the black levels of the level-adjusted chrominance and luminance signals, a chrominance signal with a predetermined relatively large dynamic range thereof modulating circuit which generates a modulated chrominance signal from the level-adjusted chrominance signal, an adding circuit which receives the modulated chrominance signal and the level-adjusted luminance signal and provides an encoded color video signal therefrom, an attenuator circuit which attenuates the encoded color video signal and a circuit for combining sync and burst signals with the attenuated encoded color video signal and with a predetermined pedestal level to provide a composite color video signal within the predetermined dynamic range.
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公开(公告)号：CA1196105A
公开(公告)日：1985-10-29
申请号：CA434737
申请日：1983-08-16
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO
IPC: H03H17/02 , G06F7/48 , G06F7/544 , G06F7/57 , G06F17/15 , G06F17/16 , H03H17/06 , H03H17/08 , H03H17/00 , G06F7/50 , G06F7/54
Abstract: DIGITAL SIGNAL PROCESSING CIRCUIT A digital signal processing circuit formed on a single integrated chip includes a multiplier for multiplying a multiplicand and multiplier signal to produce a multiple bit product signal having higher order bits delayed more than lower order bits; a first delay circuit for concatenating and delaying the multiplier and multiplicand signals to produce a delayed concatenated signal having higher order bits delayed more than lower order bits; a first selector for selectively supplying either the product signal, the delayed concatenated signal, or a concatenated signal formed from the multiplier and multiplicand signals, as a first selected signal; an adder for adding an input signal to the first selected signal to produce a summed signal; a second delay circuit for delaying a summand signal by a predetermined amount to produce a first delayed summand signal; a third delay circuit for delaying the summand signal to produce a second delayed summand signal having higher order bits delayed more than lower order bits; a second selector for selectively supplying either the first or second delayed summand signal to the adder as the input signal; a fourth delay circuit for delaying the the summand signal by a predetermined amount to produce a first delayed summed signal; a fifth delay circuit for delaying the summed signal to produce a second delayed summed signal having lower order bits delayed more than higher order bits; and a third selector for selectively supplying either the first or second delayed summed signal as an output of the processing circuit.
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公开(公告)号：DE3585593D1
公开(公告)日：1992-04-16
申请号：DE3585593
申请日：1985-11-13
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO , YAMAZAKI TAKAO
Abstract: A digital filter comprising, an input terminal provided with an input digital signal, a delay circuit connected to the input terminal and for producing a plurality of delayed digital signals each having different delay time with respect to the input digital signal, a first circuit for selectively adding the input digital signal and/or the plurality of delayed digital signals to be multiplied with one or more digital coefficient signals of same value so as to produce one or more added digital signals, a circuit for multiplying the one or more respective digital coefficient signals to the one or more added digital signals and/or one or more of the plurality of delayed digital signals, respectively a plurality of multiplied digital signals, second circuit for adding the plurality of multiplied digital signals so as to produce an output digital signal, and a circuit connected between the delay circuit and a circuit for multiplying and for increasing the one or more added digital signals and/or the one or more of the plurality of delayed digital signals in the value thereof by one or more predetermined numbers of times, whereby the one or more respective digital coefficient signals have inversely proportional values corresponding to the one or more predetermined numbers of times of the values of the one or more added digital signals and/ or the one or more of the plurality of delayed digital signals.
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公开(公告)号：DE3373768D1
公开(公告)日：1987-10-22
申请号：DE3373768
申请日：1983-06-14
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO , KOMORI SHINICHI
Abstract: An analog to digital converting system for a video signal is disclosed in which an analog video signal is fed to an analog to digital converter, then converted to a digital video signal, a digital burst signal is extracted from the digital video signal thus converted, the digital burst signal is multiplied by first and second AC signals having the same frequency as the burst frequency but different in phase to each other to produce first and second digital product signals, first and second digital signals representing DC components are derived from the first and second digital product signals, and the first and second digital signals are calculated to thereby control the phase of the sampling clock at the analog to digital converter.
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Patent Agency Ranking
公开(公告)号：CA1203891A
公开(公告)日：1986-04-29
申请号：CA430620
申请日：1983-06-17
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO , ASAIDA TAKASHI , NAGUMO FUMIO
Abstract: DIGITAL COLOR VIDEO SIGNAL ENCODER A digital encoder for use with digital luminance and chrominance signals having black levels includes a level adjusting circuit which adjusts the chrominance and luminance signals to establish a predetermined relationship between the black levels of the level-adjusted chrominance and luminance signals, a chrominance signal modulating circuit which generates a modulated chrominance signal from the level-adjusted chrominance signal, an adding circuit which receives the modulated chrominance signal and the level-adjusted luminance signal and providing an encoded color video signal therefrom, and an attenuator circuit which attenuates the encoded color video signal.
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公开(公告)号：DE69131938D1
公开(公告)日：2000-03-02
申请号：DE69131938
申请日：1991-11-29
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO
IPC: H04N11/04 , G06T7/20 , G06T9/00 , H04N1/41 , H04N1/415 , H04N5/14 , H04N19/119 , H04N19/139 , H04N19/176 , H04N19/196 , H04N19/42 , H04N19/423 , H04N19/426 , H04N19/503 , H04N19/51 , H04N19/60 , H04N19/61 , H04N19/625 , H04N7/30 , H04N7/50
Abstract: A motion vector detection apparatus comprises a delay circuit for receiving first picture data and for outputting a particular detection range of picture data, a block comparison circuit for receiving both second picture data with a particular time difference from the first picture data and picture data from the delay circuit and for detecting a difference between picture data from the delay circuit and second picture data for each block of P x Q picture elements, and a determination circuit for determining a degree of matching of a picture of an output signal from the block comparison circuit. The delay circuit comprises a scanning conversion circuit for converting input picture data from conventional horizontal scanning into scanning within the block, and a number of shift registers for receiving the first picture data with a delay of one frame. The shift registers are arranged such that both a first block of P x Q picture elements which are earlier than a particular reference tap of the shift registers and a second block which deviates by i picture elements horizontally and by j picture elements vertically from the first block are set, and such that when the first block does not deviate from the second block, a tap with a delay which is equal to the difference between each picture element of the second block and the reference tap is selected, the second picture data being obtained from the selected tap.
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公开(公告)号：CA2246536A1
公开(公告)日：1998-07-09
申请号：CA2246536
申请日：1997-12-25
Applicant: SONY CORP
Inventor： KONDO YOSHIHITO , IWASE SEIICHIRO , KUROKAWA MASUYOSHI , OKUDA HIROSHI
Abstract: The characteristic of nonlinear processing of image data are designated by means of a GUI and the processing results are immediately displayed. A personal computer (72) displays a GUI image for input on a monitor. When a user designates a nonlinear characteristic through an input device (70), the computer (72) extracts a polygonal line function representing the nonlinear characteristic and displays the function in the GUI image. In addition, the computer (72) generates a program used when a linear array type multipleparallel processor (DSP80) executes the nonlinear processing specified by the extracted polygonal line function and downloads the program in the processor (DSP80).
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公开(公告)号：DE69121732D1
公开(公告)日：1996-10-10
申请号：DE69121732
申请日：1991-01-25
Applicant: SONY CORP
Inventor： IWASE SEIICHIRO
IPC: G06F15/173 , G06T1/20
Abstract: An image signal processing circuit which comprises a multiple port memory and a plurality of processor elements connected to the multiple port memory, wherein the write address and/or read address of each of the processor elements are set to the multiple memory in a given address area. A register, a delay circuit and/or a buffer memory are/is formed among the processor elements in accordance with the setting of the write address and/or read address.
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公开(公告)号：DE3586291T2
公开(公告)日：1993-02-25
申请号：DE3586291
申请日：1985-04-11
Applicant: SONY CORP
Inventor： SHIROTA NORIHISA , YAMAZAKI TAKAO , IWASE SEIICHIRO
Abstract: There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit (11, 51). A signal selecting circuit (12) is divided into N first unit selecting circuits (21, 22, 23, 24) and a second unit selecting circuit (25). M of the output signals of a shift register (R 1 , R 2 , ...) are inputted to the first unit selecting circuits (21, 22, 23, 24), by which one of them is selected. The outputs of the N first unit selecting circuits (21, 22, 23, 24) are supplied to the second unit selecting circuit (25), by which one of them is selected. A pipeline process is performed by inserting a delay circuit (R 21 , R 22 , R 23 , R 2 4) to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit (25). Further, the selecting signal can be made variable for every one clock and a delay circuit (33,37) is inserted on the output side of a selecting signal forming circuit (13). With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.
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