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公开(公告)号：DE69526685D1
公开(公告)日：2002-06-13
申请号：DE69526685
申请日：1995-08-29
Applicant: SONY CORP
Inventor： OHKI MITSUHARU , HASHIGUCHI AKIHIKO , YAMAZAKI TAKAO , KUROKAWA MASUYOSHI
Abstract: A parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of individual processors. For signals comprised of data of a length, serving as the unit of processing, of m or less and n or more, these parallel processors are connected and used as a single parallel processor apparatus which performs processing equivalent to that by a conventional parallel processor apparatus. For signals comprised of data of a length of n or less, these parallel processors are independently used to perform pipeline processing and thereby perform two times the amount of processing of that performed by a conventional parallel processor apparatus.
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公开(公告)号：DE602005001967T2
公开(公告)日：2008-04-30
申请号：DE602005001967
申请日：2005-03-24
Applicant: SONY CORP
Inventor： MICHEL XAVIER , NISHIBORI KAZUHIKO , AOYAMA KOJI , KUROKAWA MASUYOSHI
Abstract: An image processing technique that calculates, Inter-field-interpolation spatial transition based on the sum of absolute values of differences between pixel values of an inter-field-interpolated pixel and adjacent pixels on the same field. Inter-field-interpolation temporal transition is calculated based on the sum of absolute values of differences between pixel values of the inter-field-interpolated pixel and pixels at corresponding positions on previous delayed field and present field. Intra-field-interpolation temporal transition is calculated based on the sum of absolute values of differences between pixel values of an intra-field-interpolated pixel and the pixels at the corresponding positions on the previous delayed field and the present field. The amounts of error in the interpolated pixels are calculated based on information of the inter-field-interpolation spatial transition, inter-field-interpolation temporal transition, and intra-field-interpolation temporal transition, and a pixel is generated by switching between inter-field interpolation and intra-field interpolation accordingly.
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公开(公告)号：DE602005001717T2
公开(公告)日：2008-03-13
申请号：DE602005001717
申请日：2005-03-24
Applicant: SONY CORP
Inventor： AOYAMA KOJI , NISHIBORI KAZUHIKO , MICHEL XAVIER , KUROKAWA MASUYOSHI
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公开(公告)号：DE602005001967D1
公开(公告)日：2007-09-27
申请号：DE602005001967
申请日：2005-03-24
Applicant: SONY CORP
Inventor： MICHEL XAVIER , NISHIBORI KAZUHIKO , AOYAMA KOJI , KUROKAWA MASUYOSHI
Abstract: An image processing technique that calculates, Inter-field-interpolation spatial transition based on the sum of absolute values of differences between pixel values of an inter-field-interpolated pixel and adjacent pixels on the same field. Inter-field-interpolation temporal transition is calculated based on the sum of absolute values of differences between pixel values of the inter-field-interpolated pixel and pixels at corresponding positions on previous delayed field and present field. Intra-field-interpolation temporal transition is calculated based on the sum of absolute values of differences between pixel values of an intra-field-interpolated pixel and the pixels at the corresponding positions on the previous delayed field and the present field. The amounts of error in the interpolated pixels are calculated based on information of the inter-field-interpolation spatial transition, inter-field-interpolation temporal transition, and intra-field-interpolation temporal transition, and a pixel is generated by switching between inter-field interpolation and intra-field interpolation accordingly.
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公开(公告)号：DE60208292D1
公开(公告)日：2006-02-02
申请号：DE60208292
申请日：2002-10-08
Applicant: SONY CORP
Inventor： HOSHINO TAKAYA , SARUGAKU TOSHIO , SOMEYA IKUO , KONDO MAKOTO , UEKI NOBUO , KUROKAWA MASUYOSHI , NISHIBORI KAZUHIKO , AOYAMA KOJI , MOGI YUKIHIKO
Abstract: An image signal processing apparatus receives an image signal which has been generated by subjecting a telecine-converted image to double speed conversion. The image signal processing apparatus is operable to process the telecine-converted image signal by forming one film frame from four fields, a first field on the basis of a difference value calculated between pixel signal levels, and shifting the position of a detected pixel in a vector direction of a motion vector such that an amount of shift is progressively increased in accordance with a transition made from the identified first field to the subsequent fields.
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Patent Agency Ranking
公开(公告)号：CA2246536A1
公开(公告)日：1998-07-09
申请号：CA2246536
申请日：1997-12-25
Applicant: SONY CORP
Inventor： KONDO YOSHIHITO , IWASE SEIICHIRO , KUROKAWA MASUYOSHI , OKUDA HIROSHI
Abstract: The characteristic of nonlinear processing of image data are designated by means of a GUI and the processing results are immediately displayed. A personal computer (72) displays a GUI image for input on a monitor. When a user designates a nonlinear characteristic through an input device (70), the computer (72) extracts a polygonal line function representing the nonlinear characteristic and displays the function in the GUI image. In addition, the computer (72) generates a program used when a linear array type multipleparallel processor (DSP80) executes the nonlinear processing specified by the extracted polygonal line function and downloads the program in the processor (DSP80).
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公开(公告)号：DE60208292T2
公开(公告)日：2006-09-07
申请号：DE60208292
申请日：2002-10-08
Applicant: SONY CORP
Inventor： HOSHINO TAKAYA , SARUGAKU TOSHIO , SOMEYA IKUO , KONDO MAKOTO , UEKI NOBUO , KUROKAWA MASUYOSHI , NISHIBORI KAZUHIKO , AOYAMA KOJI , MOGI YUKIHIKO
Abstract: An image signal processing apparatus receives an image signal which has been generated by subjecting a telecine-converted image to double speed conversion. The image signal processing apparatus is operable to process the telecine-converted image signal by forming one film frame from four fields, a first field on the basis of a difference value calculated between pixel signal levels, and shifting the position of a detected pixel in a vector direction of a motion vector such that an amount of shift is progressively increased in accordance with a transition made from the identified first field to the subsequent fields.
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公开(公告)号：DE69521464T2
公开(公告)日：2002-01-17
申请号：DE69521464
申请日：1995-08-16
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI , YAMAZAKI TAKAO
Abstract: A parallel processor for processing of an input signal having a plurality of pieces of data per period, comprises a plurality of unitary processing units provided in parallel in a number corresponding to the plurality of pieces of data and performing processing for each piece of data. Each of the unitary processing units enables the exchange of data with the two adjoining unitary processing units, and includes a memory circuit and a processor element connected to the memory circuit. Each of the processor elements includes a full adder, a logical operation circuit for performing a logical operation on two inputs connected to a first input of said full adder, a first selector circuit for selecting one of a first data from a memory circuit in the unitary processing unit and a first data from a memory circuit in an adjoining unitary processing unit, a second selector circuit for selecting one of a second data from a memory circuit in the unitary processing unit and a second data from a memory circuit in an adjoining unitary processing unit, a third selector circuit for selecting one of the second data selected by the second selector circuit, the logical value 1, and the logical value 0 and outputting the same as a first input for the logical operation circuit, a fourth selector circuit for selecting one of the first data selected by the first selector circuit, the logical value 1, and the logical value 0 and outputting the same as a second input for the logical operation circuit, a fifth selector circuit for selecting one of the second data selected by the second selector circuit, the logical value 1, and the logical value 0 and outputting the same as a second input for the full adder, and a sixth selector circuit for selecting one of the carrier output of the full adder, the logical value 1, and the logical value 0 and outputting the same as a third input for the full adder.
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公开(公告)号：DE69521464D1
公开(公告)日：2001-08-02
申请号：DE69521464
申请日：1995-08-16
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI , YAMAZAKI TAKAO
Abstract: A parallel processor for processing of an input signal having a plurality of pieces of data per period, comprises a plurality of unitary processing units provided in parallel in a number corresponding to the plurality of pieces of data and performing processing for each piece of data. Each of the unitary processing units enables the exchange of data with the two adjoining unitary processing units, and includes a memory circuit and a processor element connected to the memory circuit. Each of the processor elements includes a full adder, a logical operation circuit for performing a logical operation on two inputs connected to a first input of said full adder, a first selector circuit for selecting one of a first data from a memory circuit in the unitary processing unit and a first data from a memory circuit in an adjoining unitary processing unit, a second selector circuit for selecting one of a second data from a memory circuit in the unitary processing unit and a second data from a memory circuit in an adjoining unitary processing unit, a third selector circuit for selecting one of the second data selected by the second selector circuit, the logical value 1, and the logical value 0 and outputting the same as a first input for the logical operation circuit, a fourth selector circuit for selecting one of the first data selected by the first selector circuit, the logical value 1, and the logical value 0 and outputting the same as a second input for the logical operation circuit, a fifth selector circuit for selecting one of the second data selected by the second selector circuit, the logical value 1, and the logical value 0 and outputting the same as a second input for the full adder, and a sixth selector circuit for selecting one of the carrier output of the full adder, the logical value 1, and the logical value 0 and outputting the same as a third input for the full adder.
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公开(公告)号：EP1460845A4
公开(公告)日：2009-10-28
申请号：EP02786103
申请日：2002-12-13
Applicant: SONY CORP
Inventor： HOSHINO TAKAYA , SARUGAKU TOSHIO , SOMEYA IKUO , KONDO MAKOTO , NISHIBORI KAZUHIKO , AOYAMA KOJI , MOGI YUKIHIKO , UEKI NOBUO , KUROKAWA MASUYOSHI
CPC classification number: H04N7/0132 , H04N5/145 , H04N7/014 , Y10S348/91
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