-
公开(公告)号：JPS60150258A
公开(公告)日：1985-08-07
申请号：JP614784
申请日：1984-01-17
Applicant: SONY CORP
Inventor： SUGIKI HIROSHI , ODAKA KENTAROU , SATAKE TOMOJI , OOMORI TAKASHI , YAMADA MAKOTO
IPC: G11B5/588 , G11B15/467
Abstract: PURPOSE:To control assuredly tracking of a rotary head by recording plural positioning signals and tracking pilot signals, the detecting the pilot signal by using the reproduction output of the positioning signal as the reference. CONSTITUTION:The tracking pilot signal and the erasion signal are recorded to a magnetic tape, and the erasion signal is used as a positioning signal. A head 1B reproduces a pilot signal PA2 of a track 5B2 and pilot signals PB2 and PB1 of adjacent tracks 5A2 and 5A1 at an area AT1. A sampling pulse corresponding to each pilot signal is formed according to erasion signals (EA2, EA4 and EA6 during a period tB). Then the peak is held for the crosstalk of the pilot signals of tracks 5A2 and 5A1. The difference of tracking signals corresponding to each crosstalk between pilot signals PB2 and PB1, PB4 and PB3 and PB6 and PB5 is obtained as a tracking control signal.
-
公开(公告)号：JPS59113517A
公开(公告)日：1984-06-30
申请号：JP22473682
申请日：1982-12-21
Applicant: Sony Corp
Inventor： ODAKA KENTAROU
CPC classification number: G11B20/10
Abstract: PURPOSE:To operate a circuit stably without requiring a high frequency clock while keeping advantages of non-adjusting, high capacity, and no specular change, by generating a clock signal digitally and using a ring oscillator, whose adjustment is unnecessary, for oscillation. CONSTITUTION:A ring oscillator 8 is constituted with a circuit 5 consisting of n pieces of cascaded delay elements 51, 52-5n, a select circuit 6, and an inverter 7. The select circuit 6 takes out selectively prescribed one of tap outputs led out from respective output terminals of n pieces of dealy elements and feed it back to the delay element 51 of the first stage of the circuit 5 through the inverter 7 and attains an output clock signal CP. The ring oscillator 8 is oscillated with an oscillation period T corresponding to the type selection of the select circuit 6. An edge pulse Ep of the rise of reproduced digital data DIN is attained by an edge detecting circuit 9, and each delay element of the circuit 5 is reset by the pulse Ep, and the period of data DIN is detected by a period detecting circuit 10, thereby controlling the tap selection of the select circuit 6.
Abstract translation: 目的：为了稳定地运行电路，不需要高频时钟，同时保持不调整，高容量和无镜面变化的优点，通过数字地产生时钟信号并使用不需要调整的环形振荡器进行振荡。 构成：环形振荡器8由由n个级联延迟元件51,52-5n，选择电路6和反相器7组成的电路5构成。选择电路6选择性地指定一个抽头输出引出 从n个去耦元件的各个输出端子通过反相器7将其馈送回电路5的第一级的延迟元件51，并获得输出时钟信号CP。 环形振荡器8以对应于选择电路6的类型选择的振荡周期T振荡。再现的数字数据DIN的上升的边缘脉冲Ep由边缘检测电路9获得，并且电路的每个延迟元件 5由脉冲Ep复位，并且周期检测电路10检测数据DIN的周期，从而控制选择电路6的抽头选择。
-
公开(公告)号：JPS59110011A
公开(公告)日：1984-06-25
申请号：JP21818282
申请日：1982-12-13
Applicant: Sony Corp
Inventor： ODAKA KENTAROU
IPC: G11B20/10
CPC classification number: G11B20/10527
Abstract: PURPOSE:To attain higher-reliability recording and reproduction when track width is widened by employing a modulation system which is compatible with the modulation system of a PCM signal in high-density recording and reproduction and has longer recording wavelength for recording and reproduction with widened track width. CONSTITUTION:The FM modulation system is employed as the modulation signal of PCM data for high-density recording wherein a tape speed is slow and tracks are formed while overlapping on each other, and the MFM system is employed as the modulation signal of PCM data when the tape speed is increased to widen the track width and guard bands are formed between tracks. When data is decoded during reproduction, attention to the 1st bits of every two bits is paid for both modulation systems to attain the demodulation by a single decoder regardless of the modulation system. Namely, the compatibility is obtained. In this case, the shortest recording wavelength of the FM modulation system is twice as long as that of the FM system. Therefore, this system is advantageous during the recording and reproduction of PCM signals with regard to a dropout, S/N ratio, etc., and highly reliable data is read out.
Abstract translation: 目的：通过采用与高密度记录和再现中的PCM信号的调制系统相兼容的调制系统来扩大轨道宽度，以获得更高可靠性的记录和再现，并且具有用于记录和再现的更长记录波长 宽度。 构成：FM调制系统被用作用于高密度记录的PCM数据的调制信号，其中磁带速度较慢并且在彼此重叠的同时形成磁道，并且MFM系统被用作PCM数据的调制信号，当 提高磁带速度以加宽轨道宽度，并且在轨道之间形成保护带。 当在再现期间对数据进行解码时，对于两个调制系统都支付对每一位的第1位的注意，以便无论调制方式如何，通过单个解码器来实现解调。 即，获得了兼容性。 在这种情况下，FM调制系统的最短记录波长是FM系统的两倍。 因此，该系统在关于丢失，S / N比等的PCM信号的记录和再现期间是有利的，并且读出高可靠性的数据。
-
公开(公告)号：JPS58158008A
公开(公告)日：1983-09-20
申请号：JP4110482
申请日：1982-03-15
Applicant: SONY CORP
Inventor： MORIO MINORU , SHIMADA KEIICHIROU , TAKAHASHI TAKAO , ODAKA KENTAROU
IPC: H04N5/91 , G11B20/00 , G11B20/10 , G11B27/02 , G11B27/032
Abstract: PURPOSE:To obtain a distinct reproduced monitoring sound, by compensating the reproduced FM signal which is dropped out by the disturbance of the recording signal in the stage of after-recording by the output of a delay circuit. CONSTITUTION:A delay circuit 18 which delays a reproduced FM audio signal by the time duration of the recording section of a PCM audio signal and a changeover switch 20 which selects the reproduced FM audio signal and the output of the delay circuit 18 are provided. Said circuit and switch are so constituted that the switch 20 can be changed over to the output side of the circuit 18 in the recording section of the PCM audio signal in the stage of recording the fresh PCM audio signal in the recording part of the PCM audio signal while reproducing the video signal and the FM audio signal, whereby the reproduced monitoring sound which is beforehand corrected with the delay output is obtained.
-
公开(公告)号：JPS58111539A
公开(公告)日：1983-07-02
申请号：JP21521781
申请日：1981-12-25
Applicant: SONY CORP
Inventor： SAKO YOUICHIROU , ODAKA KENTAROU , IGA AKIRA
Abstract: PURPOSE:To process efficiently signals, by providing pointers which correct and represent errors if a block has errors of a prescribed word and bit after classifying the error in response to the error bit number and discriminating the pointers at the next stage. CONSTITUTION:Two-word error correction is executed at the decoder of the prestage, and a plurality (P1, P2, P3) of error pointers to bits constituting the word are provided, an error discriminating code is given to the error pointers, and error correction is done at the decoder of the next stage by using the error pointers. First, the decoder of the next stage discriminates error bits by using a parity syndrome Sp and the number of error pointers P1, P2 and P3 included in bits of one word unit are counted. The error correction is classified through the number of errors, and based on the range of error correction represented with the parity syndrome Sp, the error correction is executed by using the error pointers P1-P3.
-
Patent Agency Ranking
公开(公告)号：JPS57155667A
公开(公告)日：1982-09-25
申请号：JP4192181
申请日：1981-03-23
Applicant: SONY CORP
Inventor： ODAKA KENTAROU
Abstract: PURPOSE:To simplify the constitution of the titled circuit and to make the circuit suitable to the IC conversion, by constituting an arithmetic circuit by combining an adder circuit with an ROM or a PLA. CONSTITUTION:The elements alpha and alpha on a Galois matter GF (2m) are supplied, and these exponents (i) and (j) are produced by a converting ROM1. An inversion control circuit 4 is provided to perform the switching between an inverse action and noninverse action of the ROM1 by a control signal CTL2. Thus either the multiplication or division can be carried out, and at the same time a time shared process is performed to require just a single unit of ROM1.
-
公开(公告)号：JPS574629A
公开(公告)日：1982-01-11
申请号：JP6760880
申请日：1980-05-21
Applicant: SONY CORP
Inventor： ODAKA KENTAROU , SAKO YOUICHIROU , IWAMOTO IKUO , DOI TOSHITADA , ROODOBUITSUKU BII FURIISU
Abstract: PURPOSE:To increase the error correcting capacity, by supplying a data series to an error correction encoder to produce the 1st check word series and supplying the 1st check word series to a correction encode circuit after giving a change to the state of array of the check word series through a delaying circuit to produce the 2nd check word series. CONSTITUTION:The PCM data series of 24 channels are supplied to an even-odd interleaver to receive a one-word delay by a one-word delaying circuit. The array of the data series is changed by the transmission channel. Then the output of the even-odd interleaver is supplied to an encoder to form the 1st check word. Thereafter, both the PCM data series and the check word series are supplied to another interleaver to carry out a delaying process after changing the position of transmission channel. The output of this interleaver is supplied to the encoder to form the 2nd check word. Thus the PCM data plus the 1st and 2nd check words are transmitted.
-
公开(公告)号：JPS56119550A
公开(公告)日：1981-09-19
申请号：JP2260580
申请日：1980-02-25
Applicant: SONY CORP
Inventor： DOI TOSHITADA , ODAKA KENTAROU
Abstract: PURPOSE:To correct the error of one or two words, by supplying respective one words of data sequences in the first and the second arragement states to adjacent coders to form a parity sequence consisting of adjacent parity words. CONSTITUTION:PCM data sequences L and R of stereo audio signal left and right channels are distributed by distributor 30 to take out 12-channel PCM data sequeces X0-X11 of the first arrangement state, and they are delayed by 3D-14D to obtain PCM data sequences Y0-Y11 of the second arragement state. Respective one words of these data sequences are supplied to adders 11 and 12, and the simple parity word is supplied to adjacent coders 21 and 22 to form an adjacent parity word. The first and second simple parity words PZ and RZ and the first and second adjacent parity words QZ and SZ are added to data sequences Z0-Z11 of the third arrangement state by mixer 40, and they are transmitted as one block, thereby correcting the error of one or two words completely.
-
公开(公告)号：JPS5694557A
公开(公告)日：1981-07-31
申请号：JP17228279
申请日：1979-12-27
Applicant: SONY CORP
Inventor： ODAKA KENTAROU
Abstract: PURPOSE:To avoid a failure such as of occurrence of abnormal sound at a connecting point, caused by malfunction resulted from the error correction made around the connecting position, by disabling the error correction in the section where two PCM signals are in mixture through deinterleave processing. CONSTITUTION:Interleave processing is made, in which PCM data of a plurality of channels (e.g., L and R) and an error correction code P to it are delayed in different times (e.g., D and 2D), and deinterleave which cancells the delay, is made, for error correction. In connecting two different PCM signals #1, #2 through the adoption of such a transmission method, connection is made through conversion processing of PCM data located before or after the connecting points E0, E1, error correction code P, or error detection code C, so that error correction can not be made in the section where #1 and #2 PCM signals are mixed by means of the deinterleave processing.
-
公开(公告)号：JPS5683154A
公开(公告)日：1981-07-07
申请号：JP15941179
申请日：1979-12-07
Applicant: SONY CORP
Inventor： ODAKA KENTAROU
Abstract: PURPOSE:To enable transmission, by detecting errors of PCM data at an error detection circuit, replacing the data into those of positive or negative peak value in detecting errors, and adding the result of error detection with the data without providing special memories. CONSTITUTION:PCM data are fed to an error detection circuit 20 with the error detection code to detect the error in PCM data. Further, if there is no error, the output of the circuit 20 makes the switch 30 as the terminal N, and the PCM data delayed by one frame at the delay circuit 80 is written in the memory 10. Further, if any error is detected, the switch 30 is switched to the terminal E and the data of positive or negative peak value is produced from the peak value data generating circuit 40, and the data with this peak value is written in the memory 10 via the switch 30. The output from this memory 10 is converted into parallel data at the serial/parallel conversion circuit 50, the error in the input data is detected with the peak value at the error data detection circuit 70 and error correction is made at an error correction circuit 60.
-
-
-
-
-
-
-
-
-
Search Results
141
records
(took 0.025 seconds)
