公开(公告)号：JP2006196642A

公开(公告)日：2006-07-27

申请号：JP2005006065

申请日：2005-01-13

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OOKA YUTAKA

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To ensure a semiconductor device including a multilayered wiring structure having high wiring reliability by forming a second insulating film which can be selectively etched to the first insulating film of a wiring layer and in which a connection hole is formed. SOLUTION: The semiconductor device comprises the first insulating film 11; a first wiring 21 formed on the first insulating film 11 and including a barrier film 22 only on the first wiring 21, and a second insulating film 12 formed on the first insulating film 11 while covering the first wiring 21 and having a connection hole 23 formed therein. The first insulating film 11 side of the second insulating film 12 is selectively etchable to the first insulating film 11. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了确保包括具有高布线可靠性的多层布线结构的半导体器件，通过形成可以选择性地蚀刻到布线层的第一绝缘膜并且形成有连接孔的第二绝缘膜 。 解决方案：半导体器件包括第一绝缘膜11; 形成在第一绝缘膜11上并仅包含在第一布线21上的阻挡膜22的第一布线21和形成在第一绝缘膜11上的第二绝缘膜12，同时覆盖第一布线21并形成有连接孔23 在其中。 第二绝缘膜12的第一绝缘膜11侧可选择性地蚀刻到第一绝缘膜11.版权所有：（C）2006，JPO＆NCIPI

公开(公告)号：JP2006073907A

公开(公告)日：2006-03-16

申请号：JP2004257881

申请日：2004-09-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OOKA YUTAKA

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To improve a device speed and a device reliability by introducing an etching stopper for preventing a coarse face of a bottom of a wiring groove to a region to be a bottom part of the wiring groove.
SOLUTION: A method for manufacturing a semiconductor device having an intelayer insulating film including a porous insulating film comprises a step of forming an insulating film pattern 17 of a material different from an insulating film 18 with a wiring layer of the interlayer insulating film formed, in a region to be a bottom part of the wiring groove 20, that is, in the region with the wiring groove on an insulating film 15 on which connecting holes are formed, before forming the wiring groove 20 on the interlayer insulating film.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了通过引入用于防止布线槽的底部的粗糙面到作为布线槽的底部的区域的蚀刻停止件来提高器件速度和器件的可靠性。 解决方案：一种制造具有包括多孔绝缘膜的智能绝缘膜的半导体器件的方法包括以下步骤：形成与绝缘膜18不同的材料的绝缘膜图案17，其中层间绝缘膜的布线层 在形成布线槽20的层间绝缘膜上形成布线槽20的底部的区域，即在形成有连接孔的绝缘膜15上的布线槽的区域中。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004172336A

公开(公告)日：2004-06-17

申请号：JP2002336103

申请日：2002-11-20

Applicant: Sony Corp ,  ソニー株式会社

Inventor： OOKA YUTAKA

IPC: H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure in which a cap film that does not worsen wiring delays is formed by using a cap film preventing the rise of wiring resistances and the diffusion of copper and consisting of an insulating film having an oxidation resistance and a hydrofluoric acid resistance on wiring at the necessary minimum.
SOLUTION: A method of manufacturing a semiconductor device includes steps of: forming a copper oxide film 21 only on the surface of wiring 15 embedded in an interlayer insulating film 12 and composed of copper or a copper alloy; selectively removing the copper oxide film 21; and forming the cap film 31 which prevents the diffusion of copper only on areas from which the copper oxide film 21 is removed.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种布线结构，其中通过使用防止布线电阻的上升和铜的扩散的覆盖膜形成不增加布线延迟的盖膜，并且由具有 抗氧化性和布线上的氢氟酸电阻必要最小。 解决方案：制造半导体器件的方法包括以下步骤：仅在嵌入在层间绝缘膜12中并由铜或铜合金构成的布线15的表面上形成氧化铜膜21; 选择性地除去氧化铜膜21; 并且形成仅防止铜氧化物膜21被除去的区域上的铜的扩散的盖膜31。 版权所有（C）2004，JPO

公开(公告)号：JP2003258088A

公开(公告)日：2003-09-12

申请号：JP2002060236

申请日：2002-03-06

Applicant: SONY CORP

Inventor： OOKA YUTAKA ,  TAKAHASHI SHINGO ,  TAI KAORI ,  NOGAMI TAKESHI ,  HORIKOSHI HIROSHI ,  KOMAI HISANORI

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To suppress deterioration in electromigration resistance and to reduce via resistance while making good use of characteristics of a barrier metal needed when, for example, Cu is used as a wiring material. SOLUTION: The method for manufacturing a semiconductor device 1 having a multi-layered wiring structure includes a barrier metal filming process of forming a 2nd inter-layer insulating film 8 on a 1st wiring layer 4 formed by burying the wiring material in a 1st inter-layer insulating film 7, forming a recess of a trench and a via hole in the 2nd inter-layer insulating film 8, and forming the barrier metal 13 in the recess and a barrier metal removing process of removing the barrier metal 13 at the via hole bottom by etching; and the barrier metal 13 at the bottom of the 2nd wiring trench is left in the barrier metal removing process. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003243392A

公开(公告)日：2003-08-29

申请号：JP2002040440

申请日：2002-02-18

Applicant: SONY CORP

Inventor： OOKA YUTAKA ,  NOGAMI TAKESHI ,  TAI KAORI ,  SEGAWA YUJI

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor device, and its fabricating method, in which a diffusion of copper is prevented surely. SOLUTION: In the inventive semiconductor device, a cap film having a copper diffusion preventive function is formed on a metallization containing copper and the surface of the cap film is silicificated. In the inventive method for fabricating a semiconductor device provided with a cap film having a copper diffusion preventive function formed on a metallization containing copper, the cap film having a copper diffusion preventive function is formed on a metallization containing copper and the surface of the cap film is silicificated. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003243389A

公开(公告)日：2003-08-29

申请号：JP2002039370

申请日：2002-02-15

Applicant: SONY CORP

Inventor： OOKA YUTAKA ,  NOGAMI TAKESHI ,  SEGAWA YUJI ,  HORIKOSHI HIROSHI

IPC: H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To realize high reliability without causing any increase in the dielectric constant. SOLUTION: An insulation film 8 of an insulation material containing no oxygen is formed selectively on a metallization 2 containing Cu buried in a trench 4 of an interlayer insulation film 3. The insulation material containing no oxygen is at least one kind selected from SiN or SiC. The fabrication method comprises a step for forming a metallization containing Cu by filling the trench of the interlayer insulation film with a metal containing Cu, and a step for forming an insulation film of an insulation material containing no oxygen selectively on the metallization containing Cu. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003239077A

公开(公告)日：2003-08-27

申请号：JP2002039096

申请日：2002-02-15

Applicant: SONY CORP

Inventor： OOKA YUTAKA ,  NOGAMI TAKESHI ,  KOMAI HISANORI ,  HORIKOSHI HIROSHI ,  SEGAWA YUJI

IPC: C23C18/31 ,  H01L21/288

Abstract: PROBLEM TO BE SOLVED: To attain energy saving. SOLUTION: The plating equipment has a plating chamber 1 in which a plating solution having prescribed film-forming temperature is held to apply film forming to a material to be treated; a plating solution supply source 3 for storing the plating solution therein, a supply pipe 2 for introducing the plating solution from the plating solution supply source 3 to the plating chamber 1, and a waste-solution pipe 4 which is connected to the plating chamber 1 to discharge the used plating solution. The waste-solution pipe 4 is brought into thermal contact with the supply pipe 2 to carry out heat exchange, by which the plating solution in the supply pipe 2 is heated. COPYRIGHT: (C)2003,JPO