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公开(公告)号：JP2001258046A
公开(公告)日：2001-09-21
申请号：JP2000068934
申请日：2000-03-13
Applicant: SONY CORP
Inventor： KAMETANI TAKASHI , YAMAMURA TAKAYA
Abstract: PROBLEM TO BE SOLVED: To obtain a video encoder with which an output composite video signal synchronizing with input digital vertical synchronizing signal accompanied by received digital luminance and chrominance signals can be obtained and the possibility of the color sequence of the output composite video signal which deviates from the color sequence of the standard television system can be precluded. SOLUTION: A synchronization processing circuit is provided with a phase shift means 213, that shifts the phase of a received digital vertical synchronizing signal delayed by a delay means 201, in matching with a phase of a sub carrier generated by a video encoder to obtain an output digital vertical synchronizing signal, and the output digital vertical synchronizing signal from the phase shift means 213 is fed to a standard horizontal synchronizing signal generating means for synchronizing the output digital horizontal synchronizing signal having a standard horizontal period with the output digital vertical synchronizing signal.
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公开(公告)号：JPH11313244A
公开(公告)日：1999-11-09
申请号：JP11749798
申请日：1998-04-27
Applicant: SONY CORP
Inventor： OTA KIYOSHI , YAMAMURA TAKAYA
Abstract: PROBLEM TO BE SOLVED: To improve function performance with a simple configuration by inserting a prescribed mark to a video image corresponding to a luminance component within a range of levels among displayed video images. SOLUTION: A digital video signal S4 is given to a finder signal processing section 8 at a period of fields in the case of photographing by using a digital video camera 1. The finder signal processing section 8 discriminates to whether or not a luminance level of the digital video signal S4 is within a level of slanted line insertion desired by the operator in a range of plural slanted line insertion levels set in advance, and then selectively gives density decision data D4 consisting of desired inserted slanted line density at a desired timing to a viewfinder 10 in place of the digital video signal S4 only when the discrimination indicates an affirmative result. As a result, a video image based on an object is displayed on the viewfinder 10 and flowing slanted lines in response to the density decision data D4 are inserted to a video image part corresponding to a range of the slanted insertion levels.
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公开(公告)号：JPH09186589A
公开(公告)日：1997-07-15
申请号：JP35181795
申请日：1995-12-27
Applicant: SONY CORP
Inventor： EZAKI KUNIHIRO , YAMAMURA TAKAYA
Abstract: PROBLEM TO BE SOLVED: To reduce a tracking time when a phase of an input signal is largely changed and to keep a period of an output signal from a subordinate frequency divider stable. SOLUTION: A frequency divider of a PLL is made up of a subordinate counter 24 and a host counter 21. The subordinate counter 20 and a decoder 23 frequency-divide a clock whose frequency is a/N into 1/L and the host counter 21 and a decoder 22 frequency-divide the clock whose frequency is a/N into 1/H. The PLL generates an output signal of a multiple of N(=L×H). When a phase change in an input signal is large, a load value, e.g. 0 from a load value control circuit 25 is loaded to the host counter 21 by using an edge detection signal of the input signal as a load signal. On the other hand, no load value is loaded to the subordinate counter 20. Thus, the tracking time of the N-multiple output with respect to a phase change of an input signal is reduced and the period of the output signal from the subordinate counter 20 is kept stable.
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公开(公告)号：JPH04209363A
公开(公告)日：1992-07-30
申请号：JP40460590
申请日：1990-12-04
Applicant: SONY CORP
Inventor： YAMAMURA TAKAYA , OKAMOTO ICHIRO , MATSUMURA OSAMU
IPC: G11B20/00
Abstract: PURPOSE:To excellently carry out signal processing by having an FM demodulator, a means obtaining a prescribed demodulating voltage, and a means carrying out prescribed signal processing to a video signal demodulated by means of the FM demodulator according to the prescribed demodulating voltage. CONSTITUTION:A regenerated signal is supplied to the FM demodulator 2 via an input terminal 1 to be demodulated, and this demodulated signal is taken out to an output terminal via a video processing circuit 3. On the other hand, the demodulated signal from the demodulator 2 is supplied to a synchronization detecting comparator 5, and further, to a holding circuit 6. The circuit 6 is sampled and held with a pulse corresponding to the period of the ampoule part of a PCM sound signal from a terminal 7. This sampled/held signal is supplied to the video processing circuit via the comparator 5. Thus, the frequency of the ampoule part forming a PCM sound part recorded in an adjacent relation to a video signal part is determined to the frequency corresponding to a prescribed voltage, and the signal processing, etc., of the video signal can be excellently carried out through the use of this voltage.
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公开(公告)号：JPH0435584A
公开(公告)日：1992-02-06
申请号：JP14252590
申请日：1990-05-31
Applicant: SONY CORP
Inventor： YAMAMURA TAKAYA
Abstract: PURPOSE:To satisfactorily prevent illegal dubbing by inserting a signal, which corresponds to an arbitrary integral conversion value of an effective picture, to a video signal and comparing the signal corresponding to the integral conversion value with the inserted signal to discriminate whether dubbing should by permitted or not. CONSTITUTION:Values obtained by multiplying signals of picture elements designated by a ROM 33 by -1 or +1 are generated in multipliers 31a to 31p and are integrated, and integral values are successively taken out and are analogized to generate a signal. This signal is inserted to a prescribed position in the vertical blanking period of the video signal to generate the video signal. For example, only the essential video signal is recorded when dubbing is inhibited, and the video signal where the signal is inserted to a prescribed position in the vertical blanking period is recorded when dubbing is permitted. Thus, it is easily discriminated whether dubbing should be permitted or not.
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Patent Agency Ranking
公开(公告)号：JPH114436A
公开(公告)日：1999-01-06
申请号：JP15547697
申请日：1997-06-12
Applicant: SONY CORP
Inventor： MIYATA KATSURO , YAMAMURA TAKAYA
IPC: H04N5/92 , H04N19/126 , H04N19/149 , H04N19/176 , H04N19/42 , H04N19/423 , H04N19/60 , H04N19/625 , H04N19/85 , H04N19/91 , H04N19/93 , H04N7/30
Abstract: PROBLEM TO BE SOLVED: To provide an image coder in which one Q number or over is used for several initial macro blocks for quantization, so as to detect whether or not an entire coded data quantity for 5 macro blocks exceeds a specified data quantity, use effectively specified coded data with a simple configuration and using the specified coded data quantity effectively so that data are quantized thereby coding an image with high image quality. SOLUTION: Image data for each macro block are quantized and coded, based on a Q number of 0-15 at 1st-16th code quantity prediction sections 122-0 -122-15 and a Q number decode section 123 detects a highest Q number N, whose quantity is less than a specified code quantity. A 17th code quantity predict section 125 - an adder 128 add a difference of a code quantity between the case of using a Q number N+1, higher than the Q number N by one and the case of using the Q number N sequentially for each macro block, when the W number N is in use, and the sum is compared with a data quantity specified by an overflow discrimination section 129. In the case that the value is the specified code quantity or below, the macro block is quantized with a Q number N+1 at a quantization section 132.
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公开(公告)号：JPH0923155A
公开(公告)日：1997-01-21
申请号：JP17118395
申请日：1995-07-06
Applicant: SONY CORP
Inventor： YAMAMURA TAKAYA
Abstract: PROBLEM TO BE SOLVED: To reduce phase jitter by including a noise shaver in a 1st loop and controlling a digital variable frequency signal generating means by a comparison output from a digital phase comparing means through the noise shaver. SOLUTION: A feedback counter 3 divides the frequency of an output clock formed by an analog VCO 10 into 1/n and outputs frequency-divided data to a digital phase comparator 4. The comparator 4 compares the phase of a reference input signal with that of the output clock supplied through the counter 3 and outputs phase error data to be a comparison data to the noise shaver 6 through a digital loop filter 5. The shaver 6 converts the plane quantized noise spectrum of the phase error data into a high frequency up spectrum. When the high frequency is suppressed by an analog loop filter 9 in an inner loop, phase jitter generated in an oscillation output, i.e., an output clock, from the VCO 10 can be reduced.
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公开(公告)号：JPH08149001A
公开(公告)日：1996-06-07
申请号：JP28627894
申请日：1994-11-21
Applicant: SONY CORP
Inventor： YAMAMURA TAKAYA , EZAKI KUNIHIRO
Abstract: PURPOSE: To provide a phase comparator which can precisely acquire the output that is synchronized with an input signal without causing any malfunction despite lack of a synchronizing signal. CONSTITUTION: A detection means 11 detects the phase information on an input signal, and an error detection means 12 detects a phase error against the input signal. A switch means 13 switches the phase error detected by the means 12 to the phase error calculated between the fixed value +Δα and -Δα and outputs them. A 1st storage means 141 stores the phase information detected by the means 11 in an amount equivalent to the past (m) times, and a 2nd storage means 143 stores the frequency comparison states in numbers equivalent to the past (m) times. A setting means 142 sets the present frequency comparison state based on the phase information detected by the means 11, the phase information stored in the means 141 and the frequency comparison states stored in the means 143. Then a selection means 144 selects the phase errors outputted from the means 13 based on the present frequency comparison state set by the means 142 and the polarity of the phase error detected by the means 12.
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公开(公告)号：JPH0590958A
公开(公告)日：1993-04-09
申请号：JP27652591
申请日：1991-09-27
Applicant: SONY CORP
Inventor： YAMAMURA TAKAYA
Abstract: PURPOSE:To stabilize the PLL which generates a clock synchronously with a horizontal synchronizing pulse of the HDTV system. CONSTITUTION:A 2nd loop in which a phase of an output signal of a digital VCO 7 and a phase of a reference signal are compared by an analog phase comparator 4, an analog VCO 12 is controlled in response to the comparison output and an output of the analog VCO 12 is fed to a clock terminal of the digital VCO 7 is provided to the PLL circuit in addition to a 1st loop, in which a phase of an input signal and a phase of a signal based on an output signal of the digital VCO 7 are compared by the digital phase comparator 4 and the digital VCO 7 is controlled by the comparison output. Thus, the PLL is equivalent to the operation as the digital PLL, the operation is made stable and a different clock is not required for the digital circuit.
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公开(公告)号：JPH0529929A
公开(公告)日：1993-02-05
申请号：JP20246691
申请日：1991-07-17
Applicant: SONY CORP
Inventor： YAMAMURA TAKAYA , OKAMOTO ICHIRO
Abstract: PURPOSE:To reduce the lock time by generating a clock having a prescribed periodic fluctuation component so as to control a VCO in response to the output thereby setting a phase comparison frequency high. CONSTITUTION:It is desirable to set a frequency compared at a phase comparator circuit 14 to a frequency as high as possible. For example the frequency 6kHz is set to 48kHz. That is, a reference clock YCK whose frequency is 44.55kHz is fed to an input terminal 11 and given to a frequency divider circuit 12. The circuit 12 receives a frame pulse FP to frequency-divide the given clock YCK by 1/928.125 to obtain a CK2 whose frequency is 48kHz, which is fed to the circuit 14. On the other hand, a clock CK3 whose center frequency is 24.576kHz from a VCO 15 is subjected to 1/512 frequency division by a frequency divider circuit 16 and its output is fed to the circuit 14 as a clock CK4 whose frequency is 48kHz. Then the clock CK4 is phase-compared with the clock CK2 from the circuit 12 with 48kHz and the result is fed to the VCO 15 via an LPF 17 to reduce the lock time.
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