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公开(公告)号：DE60036445T2
公开(公告)日：2008-06-19
申请号：DE60036445
申请日：2000-10-11
Applicant: SONY CORP
Inventor： YAMAOKA NOBUSUKE , OKAMOTO ICHIRO , SAITO TAKEHIKO , KOTANI YASUTAKA , NIKATA KENJI
Abstract: There are provided the delay coarse adjustment circuit 3, the delay fine adjustment circuit 4, and the inverter circuit 5. The delay coarse adjustment circuit 3 stepwise varies a delay amount based on the delay coarse adjustment signal S11 and supplies the input oscillation signal S12 with a coarse delay. The delay fine adjustment circuit 4 stepwise varies a delay amount based on the delay fine adjustment signal S2 and supplies the input oscillation signal S13 with a fine delay which is smaller than a delay amount supplied by the delay coarse adjustment circuit 3. The inverter circuit 5 inputs the oscillation signal S14 from the delay coarse adjustment circuit 3 or the delay fine adjustment circuit 4. The delay coarse adjustment circuit 3 coarsely adjusts delays. The delay fine adjustment circuit 4 fine adjusts delays. The coarse and fine adjustments provide a precision delay to generate the oscillation output signal S15. The delay coarse adjustment circuit 3, the delay fine adjustment circuit 4, and the inverter circuit 5 are connected in a ring for stepwise controlling an oscillation signal's oscillation frequency.
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公开(公告)号：DE69325342T2
公开(公告)日：1999-11-04
申请号：DE69325342
申请日：1993-11-19
Applicant: SONY CORP
Inventor： INOUE HAJIME , ISHIMARU HIROYUKI , SHIMA HISATO , OGAWA KAZUYUKI , OGURO MASAKI , OKAMOTO ICHIRO
IPC: G11B20/10 , G11B20/18 , G11B27/032 , H04N5/91 , H04N5/92 , H04N9/804 , H04N9/888 , H04N9/80 , H04N9/88 , G11B5/86
Abstract: A method of dubbing compressed digital video signals (32) adopted for an apparatus (1-15) for efficient coding and subsequent recording/playback of video signals. In the method of dubbing compressed digital video signals, on a playback unit side (8-15), after padding error data by an error processing circuit with respect to an error uncorrectable in error correction by an ECC circuit (10) of playback, the digital video signal is provided with a parity for transmission by a parity generating circuit (6) and is then transmitted to a recording unit side (1-7). On the other hand, on the recording unit side (1-7), after padding error data by an error processing circuit with respect to an error uncorrectable in error correction by an ECC circuit (10) of transmission, the digital video signal is provided with a parity for recording by a parity generator (6) and is then recorded in a recording medium.
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公开(公告)号：CA2098360A1
公开(公告)日：1993-12-17
申请号：CA2098360
申请日：1993-06-14
Applicant: SONY CORP
Inventor： INOUE HAJIME , OKAMOTO ICHIRO
IPC: G11B20/12 , G11B20/18 , G11B27/032 , G11B27/036 , G11B27/30 , H04N9/806 , H04N9/888 , G11C19/02
Abstract: PATENT 450100-2793 Each track on a recording medium has a video area used for recording video and audio data, and an audio area used exclusively for recording audio data. The audio area has two regions used for recording odd-numbered audio data segments and even-numbered audio data segments, respectively. The data recorded in one of the two regions may be interleaved to further reduce vulnerability of the audio data to errors. Parity data for the audio data is recorded in a third region located between the first and second regions in each track. The audio data represents a left and a right channel. The left channel audio data is recorded in a first set of consecutive tracks, and the right channel audio data is recorded in a second set of consecutive tracks. BP15:2793.APP
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公开(公告)号：DE60036445D1
公开(公告)日：2007-10-31
申请号：DE60036445
申请日：2000-10-11
Applicant: SONY CORP
Inventor： YAMAOKA NOBUSUKE , OKAMOTO ICHIRO , SAITO TAKEHIKO , KOTANI YASUTAKA , NIKATA KENJI
Abstract: There are provided the delay coarse adjustment circuit 3, the delay fine adjustment circuit 4, and the inverter circuit 5. The delay coarse adjustment circuit 3 stepwise varies a delay amount based on the delay coarse adjustment signal S11 and supplies the input oscillation signal S12 with a coarse delay. The delay fine adjustment circuit 4 stepwise varies a delay amount based on the delay fine adjustment signal S2 and supplies the input oscillation signal S13 with a fine delay which is smaller than a delay amount supplied by the delay coarse adjustment circuit 3. The inverter circuit 5 inputs the oscillation signal S14 from the delay coarse adjustment circuit 3 or the delay fine adjustment circuit 4. The delay coarse adjustment circuit 3 coarsely adjusts delays. The delay fine adjustment circuit 4 fine adjusts delays. The coarse and fine adjustments provide a precision delay to generate the oscillation output signal S15. The delay coarse adjustment circuit 3, the delay fine adjustment circuit 4, and the inverter circuit 5 are connected in a ring for stepwise controlling an oscillation signal's oscillation frequency.
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公开(公告)号：DE69325342D1
公开(公告)日：1999-07-22
申请号：DE69325342
申请日：1993-11-19
Applicant: SONY CORP
Inventor： INOUE HAJIME , ISHIMARU HIROYUKI , SHIMA HISATO , OGAWA KAZUYUKI , OGURO MASAKI , OKAMOTO ICHIRO
IPC: G11B20/10 , G11B20/18 , G11B27/032 , H04N5/91 , H04N5/92 , H04N9/804 , H04N9/888 , H04N9/80 , H04N9/88 , G11B5/86
Abstract: A method of dubbing compressed digital video signals (32) adopted for an apparatus (1-15) for efficient coding and subsequent recording/playback of video signals. In the method of dubbing compressed digital video signals, on a playback unit side (8-15), after padding error data by an error processing circuit with respect to an error uncorrectable in error correction by an ECC circuit (10) of playback, the digital video signal is provided with a parity for transmission by a parity generating circuit (6) and is then transmitted to a recording unit side (1-7). On the other hand, on the recording unit side (1-7), after padding error data by an error processing circuit with respect to an error uncorrectable in error correction by an ECC circuit (10) of transmission, the digital video signal is provided with a parity for recording by a parity generator (6) and is then recorded in a recording medium.
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Patent Agency Ranking
公开(公告)号：AT138523T
公开(公告)日：1996-06-15
申请号：AT91308370
申请日：1991-09-13
Applicant: SONY CORP
Inventor： FUKUMOTO KENJI , OKAMOTO ICHIRO , YAMASHITA KEITARO
Abstract: Disclosed are an audio signal recording apparatus and method for recording in a plurality of tracks (T) a video signal and an audio signal of say four channels corresponding to the video signal, the tracks constituting one segment. The audio signal is recorded in a recording area (PA) separate from that (VA) for the video signal on a tape (4). The audio signal of the four channels is divided into groups each associated with a plurality of channels. Each group of audio data is recorded in one of audio signal recording blocks (PA12, PA34) obtained by dividing the audio signal recording area (PA) in the longitudinal direction of the tracks (T). The groups of audio data are each given a priority depending on the importance of the data, and data of high priorities are recorded in blocks (PA12) that are farther away from the track ends where the contact between tape (4) and head (1, 2) may be unstable.
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7.发明专利Destination guide device, its method, program and recording medium recorded with the same 审中-公开目的地指导装置，其方法，记录的程序和记录介质
公开(公告)号：JP2003083762A
公开(公告)日：2003-03-19
申请号：JP2001277792
申请日：2001-09-13
Inventor： HIDAI TAKESHI , OKAMOTO ICHIRO , NAKADA SHINGO , KATAOKA MASAKI , SUGA YOSHITAKA
Abstract: PROBLEM TO BE SOLVED: To grasp how a user moves in order to easily go to a destination.
SOLUTION: A direction (north east) of the destination 32 viewed from the user 30 is found to find a direction (east) of the user 30 from a destination guide device 1. In order to display an advance direction (right oblique back) to the destination 32 viewed from the user 30 on a display part 114, the user 30 can find only the advance direction to the destination 32. Thus, since time sorting other wasteful information is not taken, it is easy to grasp how the user 30 moves in order to go to the destination 32.
COPYRIGHT: (C)2003,JPOAbstract translation: 要解决的问题：要了解用户如何移动以便轻松前往目的地。 解决方案：从用户30看到的目的地32的方向（东北）被发现从目的地导向装置1找到用户30的方向（东））。为了显示提前方向（右斜后方）到 在显示部114上从用户30观看的目的地32，用户30只能找到到达目的地32的前进方向。因此，由于不采取其他浪费信息的时间排序，因此很容易掌握用户30如何移动 为了去目的地32。
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公开(公告)号：JPH09161417A
公开(公告)日：1997-06-20
申请号：JP33593895
申请日：1995-11-30
Applicant: SONY CORP
Inventor： OKAMOTO ICHIRO , OZAWA KAZUHIKO , MIYAI ISAO , NAKAMURA SHINJI
Abstract: PROBLEM TO BE SOLVED: To properly interpolate error data when reproducing a digital audio signal. SOLUTION: Reproduced audio data are supplied to a product-sum operation circuit 23 of a concealing circuit 10 and a conceal flag indication the presence or absence of the error of each sample of data is supplied to an error pattern detection circuit 24. A coefficient according to the detected error pattern is read from a coefficient memory 25. The product-sum operation circuit 23 generates an interpolated value according to a first-order or higher-order interpolation expression using proper samples and coefficients before and after the sample to be interpolated.
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公开(公告)号：JPH06165105A
公开(公告)日：1994-06-10
申请号：JP31247492
申请日：1992-11-20
Applicant: SONY CORP
Inventor： INOUE HAJIME , ISHIMARU HIROYOSHI , SHIMA HISATO , OGAWA KAZUYUKI , OGURO MASAKI , OKAMOTO ICHIRO
Abstract: PURPOSE:To make it possible to dub a compressed digital video signal at a low transmission rate without deteriorating image quality in a device for recording and reproducing a video signal by highly efficiently coding. CONSTITUTION:On the reproducer side, an error processing circuit 102 pads error information in an error which can not be corrected by the error correcting processing of a reproducing ECC circuit 102 and a parity generator 132 adds a transmitting parity to the error and transmits the parity-added information to the recording side. On the recorder side, an error processing circuit 127 pads error information in an error which can not be corrected by the correcting processing of a transmitting EEC circuit 121 and a parity generator 131 adds a recording parity to the error information and records the parity-added information in a recording medium.
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公开(公告)号：JPH0529929A
公开(公告)日：1993-02-05
申请号：JP20246691
申请日：1991-07-17
Applicant: SONY CORP
Inventor： YAMAMURA TAKAYA , OKAMOTO ICHIRO
Abstract: PURPOSE:To reduce the lock time by generating a clock having a prescribed periodic fluctuation component so as to control a VCO in response to the output thereby setting a phase comparison frequency high. CONSTITUTION:It is desirable to set a frequency compared at a phase comparator circuit 14 to a frequency as high as possible. For example the frequency 6kHz is set to 48kHz. That is, a reference clock YCK whose frequency is 44.55kHz is fed to an input terminal 11 and given to a frequency divider circuit 12. The circuit 12 receives a frame pulse FP to frequency-divide the given clock YCK by 1/928.125 to obtain a CK2 whose frequency is 48kHz, which is fed to the circuit 14. On the other hand, a clock CK3 whose center frequency is 24.576kHz from a VCO 15 is subjected to 1/512 frequency division by a frequency divider circuit 16 and its output is fed to the circuit 14 as a clock CK4 whose frequency is 48kHz. Then the clock CK4 is phase-compared with the clock CK2 from the circuit 12 with 48kHz and the result is fed to the VCO 15 via an LPF 17 to reduce the lock time.
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