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    VIDEO SIGNAL RECORDING REPRODUCING SYSTEM AND METHOD AND SYSTEM FOR VIDEO SIGNAL REPRODUCTION
    3.
    发明专利
    VIDEO SIGNAL RECORDING REPRODUCING SYSTEM AND METHOD AND SYSTEM FOR VIDEO SIGNAL REPRODUCTION 失效

    公开(公告)号：JP2000032377A

    公开(公告)日：2000-01-28

    申请号：JP17350299

    申请日：1999-06-21

    Applicant: SONY CORP

    Inventor： NUMAKURA TOSHIHIKO ,  YAMAMURA TAKAYA

    IPC: H04N5/91

    Abstract: PROBLEM TO BE SOLVED: To make it possible to obtain sufficient reliability in making a reproducing video signal adaptive to a picture monitor and not adaptive to other recording systems by constituting a device so that a read video signal is added to a pulse signal in a blanking period part and the reproducing video signal can be obtained. SOLUTION: In a recording system, a video signal is added to a dubbing disable discrimination signal and recorded in a storage medium. In a reproducing system, read-out of a video signal recorded in the recording medium is performed and, when the read-out video signal is the one with a dubbing disable discrimination signal added, the read-out video signal is reproduced as the one with a pulse signal having a specified level added to a blanking period part and a reproduction video signal is obtained. In the recording system of this system, at an addition part 18, a complex synchronizing signal Ds and a dubbing disable discrimination signal Dd from a dubbing disable discrimination signal/synchronizing signal generation part 19 are added to a digital video signal Dv' conducted from a memory.

    DIGITAL PLL CIRCUIT
    4.
    发明专利
    DIGITAL PLL CIRCUIT 失效

    公开(公告)号：JPH11341306A

    公开(公告)日：1999-12-10

    申请号：JP14340598

    申请日：1998-05-25

    Applicant: SONY CORP

    Inventor： OKAMOTO ICHIRO ,  YAMAMURA TAKAYA ,  KOTANI YASUTAKA ,  YOSHIOKA SHINGO

    IPC: H04N5/12 ,  H03L7/10

    Abstract: PROBLEM TO BE SOLVED: To reduce response time until a PLL is locked and also to reduce the scale of a circuit. SOLUTION: This digital PLL circuit, which produces an output signal of a frequency nfref by making the frequency fref of a reference input signal n times, has a 1st loop provided with an analog phase comparing means 6 which performs phase comparison of the reference pilot signal of a frequency f/m that is externally supplied with the feedback pilot signal of a frequency, that undergoes m frequency division of an output signal by a variable frequency dividing means 5 and controls the frequency of the output signal and a 2nd loop, which is provided with a digital frequency comparing means 2 that counts an output signal in each cycle of the reference input signal and produces a difference with the (n) as a stage number and a noise shaper 4 which integrates the stage number and calculates it for every cycle of the feedback pilot signal and controls the frequency of the output signal by changing the frequency division ratio of the means 5 of a 1st loop through the shaper 4.

    MEMORY CONTROL CIRCUIT
    6.
    发明专利
    MEMORY CONTROL CIRCUIT 失效

    公开(公告)号：JPH05219480A

    公开(公告)日：1993-08-27

    申请号：JP4616592

    申请日：1992-01-31

    Applicant: SONY CORP

    Inventor： YAMAMURA TAKAYA

    IPC: H04N5/956 ,  H04N5/95 ,  H04N9/89 ,  H04N9/896

    Abstract: PURPOSE:To cope with the passing of a reading address over a writing address by switching a field memory to be read into the other field memory when an address difference between the writing address and the reading address is within a prescribed value. CONSTITUTION:An address difference between the writing address and the reading address from a writing address generating circuit 57 and a reading address generating circuit 59 is detected by an address difference detecting circuit 62, and the output is supplied to a comparator circuit 63. The prescribed value is applied from a terminal 64 to the comparator circuit 63, and the output of the comparator circuit 63 is supplied to a switch control circuit 53. Switches 52 and 55 are switched by each one field by a field identification signal from the terminal 61. When the reading address approaches the writing address, and the difference between the reading address and the writing address is within the prescribed value, the output of the comparator circuit 63 is changed. At that time, the switch 55 is switched, and the data of the other field memory at an equal part to a screen position which is being read.

    EMPHASIS CIRCUIT
    7.
    发明专利
    EMPHASIS CIRCUIT 失效

    公开(公告)号：JPH05219475A

    公开(公告)日：1993-08-27

    申请号：JP4616492

    申请日：1992-01-31

    Applicant: SONY CORP

    Inventor： YAMAMURA TAKAYA

    IPC: G11B20/02 ,  H04N5/205 ,  H04N5/92 ,  H04N5/922

    Abstract: PURPOSE:To save the circuit scale by connecting a divergence type IIR digital filter and an FIR digital filter to suppress the divergence of the IIR digital filter in cascade so as to form a backward emphasis circuit. CONSTITUTION:Since the divergence IIR digital filter 3 includes a positive feedback loop, when the filter receives an input signal, the filter is in divergence till overflow takes place. On the other hand, an FIR digital filter 2 connecting to the pre-stage of the digital filter 3 suppresses the divergence of the IIR digital filter 3. Thus, overflow of the filter 3 is suppressed. Furthermore, a reset signal is fed to an input terminal 4 for, e.g. the horizontal blanking period so as to prevent overflow in the initial state to reset a register of the filter 3. That is, The characteristic of the backward emphasis is approximated by utilizing the divergence characteristic of the divergence type IIR digital filter.

    Clock reproducing apparatus
    8.
    发明专利
    Clock reproducing apparatus 审中-公开
    时钟再现设备

    公开(公告)号：JP2003037498A

    公开(公告)日：2003-02-07

    申请号：JP2001221771

    申请日：2001-07-23

    Applicant: Sony Corp ,  ソニー株式会社

    Inventor： YAMAMURA TAKAYA ,  YAMAOKA SHINSUKE ,  KOTANI YASUTAKA ,  OSABE HISAO

    IPC: G11B20/10 ,  G11B20/14 ,  H03L7/087 ,  H03L7/113

    Abstract: PROBLEM TO BE SOLVED: To provide a clock reproducing apparatus that can be made to not to detect frequency errors with sample data, without being affected by fold back of frequency. SOLUTION: The clock reproducing apparatus has a phase-locked loop, comprising components 1, 2, 3, 4, 5 that uses a digital signal processing circuit for receiving sample data, resulting from sampling a reproduced signal with a reproduced clock reproduced by the clock reproducing apparatus for controlling an oscillating means so as to oscillate the reproduced clock without a phase difference from a reproduced input; and a frequency-locked loop, comprising components 6, 7, 8, 9, 10, 11 that detects frequency errors between the recovered signal and the recovery clock and locks the frequency without causing no frequency error. Since the clock reproducing apparatus reproduces a clock synchronously with the reproduced signal, the clock reproduces compares a pattern of a reproduced signal waveform with a preset pattern, so as to limit the reproduced signal pattern for detecting frequency and to avoid frequency misdetection by the sample data, without being affected by fold back of frequency.

    Abstract translation: 要解决的问题：提供一种时钟再现装置，其可以使得不用样本数据检测频率误差，而不受频率折回的影响。 解决方案：时钟重放装置具有一个锁相环，包括使用数字信号处理电路接收采样数据的分量1,2,3,4,5，该数据信号处理电路是由再生时钟再现的再生信号 再现装置，用于控制振荡装置，以使得再现的时钟振荡而不与再现的输入相位相差; 以及包括检测恢复信号和恢复时钟之间的频率误差并且锁定频率而不引起频率误差的组件6,7,8,9,10,11的频率锁定环。 由于时钟再现装置与再现信号同步地再现时钟，所以时钟再现将再现信号波形的模式与预设模式进行比较，以限制用于检测频率的再现信号模式，并且避免样本数据的频率误差检测 ，而不受频率折叠的影响。

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