公开(公告)号：FR2802012B1

公开(公告)日：2002-02-15

申请号：FR9915435

申请日：1999-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  DOISE DAVID

IPC: G06F12/08 ,  G06F12/0893 ,  G11C7/10 ,  G11C7/22 ,  G06F12/06

Abstract: A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.