公开(公告)号：FR2903219A1

公开(公告)日：2008-01-04

申请号：FR0605988

申请日：2006-07-03

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL

IPC: G11C11/406 ,  H03M13/03

Abstract: L'invention vise un procédé de rafraîchissement d'une mémoire vive dynamique couplée à un système de correction d'erreur qui utilise un code correcteur d'erreur, ladite mémoire comprenant des groupes de cellules-mémoire aptes à stocker des bits, chaque groupe de cellules-mémoire étant subdivisé en paquets de cellules-mémoire. A chaque paquet de cellules-mémoire sont adjoints quelques bits formant ledit code correcteur d'erreur. On effectue sur chaque groupe de cellules-mémoire, un test de rétention dans lequel on sauvegarde le groupe sous test dans une zone mémoire sûre, après une correction de ses éventuelles erreurs par ledit système de correction d'erreur, de façon à obtenir un groupe modèle comportant des paquets modèles (étape 32) ; on effectue au bout d'une période de latence, une comparaison bit-à-bit entre le groupe modèle et ledit groupe n'ayant ni été corrigé ni rafraîchi pendant ladite période de latence ; on détecte dans chaque paquet dudit groupe, les bits dits erronés ayant des valeurs différentes de celles des bits du paquet modèle correspondant et on considère ledit paquet comme erroné s'il comporte un nombre de bits erronés supérieur à une valeur limite inférieure ou égale au nombre de bits capable d'être corrigés par le système de correction d'erreur (étape 39), et on augmente la valeur de la fréquence de rafraîchissement de la mémoire, si le nombre de groupes de cellules-mémoire comportant au moins un paquet erroné, est supérieur à un seuil fixé (étape 40a).

公开(公告)号：FR2879337A1

公开(公告)日：2006-06-16

申请号：FR0413334

申请日：2004-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL

IPC: G11C11/4093 ,  G06F12/16 ,  G11C7/10

Abstract: Circuit mémoire à double port ayant un plan mémoire comportant au moins un premier et un second module (1-1, 1-n) constitué chacun d'un réseau de cellules mémoires organisées en lignes et en colonnes, chaque ligne dudit plan mémoire permettant le stockage d'une page de mots, chaque mot de ladite page étant identifié par une adresse organisée suivant une division hiérarchique définie par (@MSB, adresse ligne, adresse colonne), avec @MSB identifiant un module particulier parmi lesdits n modules, Le circuit comporte un premier bus d'adresses (41) et un second bus d'adresses (51), ainsi qu'un premier et second bus de données (53, 54) servant respectivement à la lecture ainsi qu'à l'écriture dans lesdits modules. Pour chaque module mémoire, on dispose un multiplexeur (4-1, 4-n) dont deux entrées sont connectés aux deux bus d'adresses. La sortie du multiplexeur est connectée à un décodeur ligne (2-1, 2-n) mais également à un premier et à un second décodeur colonnes correspondants au premier et au second bus de données. Chaque multiplexeur est commandé de manière à permettre l'écriture et la lecture simultanée dans deux modules distincts.Le circuit est particulièrement adapté à l'intégration d'un code correcteur d'erreur.

公开(公告)号：DE69713868T2

公开(公告)日：2003-02-27

申请号：DE69713868

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has a dedicated circuit which concatenates variable length codes, extracts variable length codes from contiguous codes and calculates a signature from a sequence of bits. The dedicated circuit uses an instruction of two parameters, the first (D) is a group of bits and the second (L) indicates the length of the first. The working register (CAT) contains the concatenation code and supplies a shift register (42) and an OR gate (44). An indicating register (46) indicates free space in the working register (CAT) and a subtracting register produces the difference. A multiplexer (52) takes the output from either the OR gate or the bit to bit gate (54) as required by the subtracting register.

公开(公告)号：FR2820874A1

公开(公告)日：2002-08-16

申请号：FR0101934

申请日：2001-02-13

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  BULONE JOSEPH

IPC: G11C7/10 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C8/00 ,  G06F12/08 ,  G11C11/40

Abstract: A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N-1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N-1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.

公开(公告)号：DE69713868D1

公开(公告)日：2002-08-14

申请号：DE69713868

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has a dedicated circuit which concatenates variable length codes, extracts variable length codes from contiguous codes and calculates a signature from a sequence of bits. The dedicated circuit uses an instruction of two parameters, the first (D) is a group of bits and the second (L) indicates the length of the first. The working register (CAT) contains the concatenation code and supplies a shift register (42) and an OR gate (44). An indicating register (46) indicates free space in the working register (CAT) and a subtracting register produces the difference. A multiplexer (52) takes the output from either the OR gate or the bit to bit gate (54) as required by the subtracting register.

公开(公告)号：DE69713867D1

公开(公告)日：2002-08-14

申请号：DE69713867

申请日：1997-12-16

Applicant: ST MICROELECTRONICS SA

Inventor： DEYGAS OLIVIER ,  HARRAND MICHEL

IPC: G06T9/00

Abstract: The microprocessor has an operator which is dedicated to calculation of a signature. The operator uses two parameters, with the first a word containing a group of bits from the sequence and the second indicating the length of the group of bits. The operator reacts to the instruction by updating a signature register. The updated signature is the remainder from a polynomial division by a polynomial generator. The dedicated operator has XOR-gates arranged in rows and columns. The number of columns corresponds to the size of the signature register and the number of rows to the maximum length of the group of bits. The appropriate row is selected in response to the second parameter and is transferred to the signature register.

公开(公告)号：FR2812417A1

公开(公告)日：2002-02-01

申请号：FR0009882

申请日：2000-07-27

Applicant: ST MICROELECTRONICS SA

Inventor： SANCHES JOSE ,  CORNERO MARCO ,  SANTANA MIGUEL ,  GUILLAUME PHILIPPE ,  DAVEAU JEAN MARC ,  LEPLEY THIERRY ,  PAULIN PIERRE ,  HARRAND MICHEL

IPC: G06F9/38 ,  G06F9/34 ,  G06F7/38

Abstract: VLIW (very large instruction word) processor (20) for execution of instructions of variable size comprising multiple elementary codes comprises: a program memory with multiple memory banks; and means for reading the program memory. Said means comprises means for applying incremental addresses in a cyclic manner to the program memory and means for filtering out codes that that do not belong to an instruction to be executed by means of parallel bits accompanying the codes. The invention also relates to a corresponding method for reading instructions of variable size.

公开(公告)号：FR2801388A1

公开(公告)日：2001-05-25

申请号：FR9914610

申请日：1999-11-19

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL

IPC: G06F12/08 ,  G06F12/0893 ,  G06F12/06 ,  G11C7/22

Abstract: An address of column is stored in a storage element (26,28) including a current request in order to make it available when the page of the current request is in one registers of cache. To access the storage element (26,28) the register of cache are used to retrieve words of the page of the current request. An Independent claim is included for: (a) a memory controller

公开(公告)号：DE602006005012D1

公开(公告)日：2009-03-19

申请号：DE602006005012

申请日：2006-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： DRUILHE FRANCOIS ,  COFLER ANDREW ,  DUTOIT DENIS ,  HARRAND MICHEL ,  EYZAT GILLES ,  FREUND CHRISTIAN

IPC: G11C11/406

Abstract: The circuit has a refresh controller (48) controlled by a clock signal, and another refresh controller operating during standby periods. A local oscillator (51) receives another clock signal whose frequency is lower than that of the former signal and corresponds to clock frequency of events of global system for mobile communication network. A voltage regulator (59) supplies a memory network during the standby periods. An independent claim is also included for a mobile phone including a mobile phone circuit with a dynamic memory comprising a control circuit.

公开(公告)号：DE602004018646D1

公开(公告)日：2009-02-05

申请号：DE602004018646

申请日：2004-01-19

Applicant: ST MICROELECTRONICS SA

Inventor： HARRAND MICHEL ,  BULONE JOSEPH

IPC: G11C11/406 ,  G11C29/00

Abstract: The method involves successively performing measurements on a selected group of memory cells (CL) at a lower measurement frequency than a refresh frequency of unselected cells such that each selected group of cells is refreshed more slowly than unselected cells of the memory. The retention times of each group of cells are successively measured, and the unselected cells are refreshed successively. An independent claim is also included for a dynamic random access memory device.