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公开(公告)号：DE69415897T2
公开(公告)日：1999-09-02
申请号：DE69415897
申请日：1994-08-29
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
Abstract: The present invention relates to a frequency synthesizer supplying a synthesised signal (NF), comprising an oscillator (10-2) supplying a high-speed clock signal (Fh) to a divider (22) which is programmable by a digital data item (C), the high-order bits (K) of the digital data item being supplied to the programmable divider and the low-order bits to an accumulator (26) interacting with the programmable divider to increment its order of division by one unit when the accumulator overflows. The synthesizer comprises: a generator 27 of n phases (NF1 to NFn) with increasing delays of the synthesised signal (NF); a circuit (29) for comparison of the content (A) of the accumulator with N ranges of possible increasing values; and a circuit (28) for selection, as synthesised signal, of the phase, the order of which corresponds to that of the range in which the content of the accumulator lies.
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公开(公告)号：DE602007001205D1
公开(公告)日：2009-07-16
申请号：DE602007001205
申请日：2007-03-29
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES , PAILLE BRUNO
Abstract: The circuit has a temporization device (221) with an input connected to an input and an output of a demodulator. A selection signal providing unit provides a selection signal (Sel) controlling a multiplexer (220) and a control device (222). A decoding circuit and another demodulator provide a decoded signal from a coded or modulated signal and corrected reputed parts of another decoded signal when the signal (Sel) is positioned for passing a signal provided by the device (221). An independent claim is also included for a decoding circuit.
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公开(公告)号：DE60041614D1
公开(公告)日：2009-04-09
申请号：DE60041614
申请日：2000-02-25
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
Abstract: A COFDM demodulator including a fast Fourier transform circuit analyzing a received signal in a window corresponding to one symbol, each symbol carrying several phase and amplitude modulated carriers, some of which are shifted in frequency in a predetermined way from one symbol to the next one to form pilots; a bidimensional filter for interpolating, from anchors corresponding to the pilots such as received from several consecutive symbols, the distortion undergone by each carrier; and a circuit for correcting the shifting of the window with respect to an optimal position. The demodulator includes a circuit for correcting each distortion according to window shifting corrections performed respectively for the symbol associated with the distortion and for the symbols associated with the anchors used to interpolate the distortion.
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公开(公告)号：FR2888076A1
公开(公告)日：2007-01-05
申请号：FR0507040
申请日：2005-07-01
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
IPC: H04N7/167
Abstract: Un Procédé de correction de l'inversion spectrale pour un récepteur dans un système de communication numérique. Le procédé permet la réception dans le récepteur d'une séquence d'apprentissage supposée connue suivant une modulation de type pi/2 BPSK ou MDP2. Le procédé comporte les étapes suivantes :- démodulation de ladite séquence d'apprentissage ;- calcul (21,22, 23) de corrélation différentielle sur un ensemble de N échantillons reçus (Rn) et présumés envoyés (Sn) pour générer un résultat ;utilisation dudit résultat pour détecter le début de trame et pour commander une inversion spectrale dans la chaîne de réception dudit récepteur avant de lancer la détection du début de trame. L'invention permet également la réalisation d'un récepteur permettant de traiter automatiquement l'inversion spectrale.
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公开(公告)号：DE69923732T2
公开(公告)日：2006-06-14
申请号：DE69923732
申请日：1999-06-15
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
IPC: H03L7/095 , H04L27/227 , H04L7/00 , H04L27/00 , H04L27/22
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Patent Agency Ranking
公开(公告)号：DE69924055T2
公开(公告)日：2006-04-13
申请号：DE69924055
申请日：1999-07-20
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
IPC: H04L27/22 , H04L27/00 , H04L27/227
Abstract: The process uses multiplication of vector angle and analysis of derivative to locate error. The procedure provides an estimation of the frequency error of a demodulator which is used to reconstruct two binary signals (I,Q) carried on two carriers of the same frequency but operating in phase quadrature. The procedure comprises the first stage of forming vectors having the successive pairs of values (I,Q) of two binary signals as components. The second stage includes applying to each vector a transformation which multiplies its angle by four, at least when it is equal to a multiple of /4, whilst retaining its modulus. The third stage includes calculating the average (x1,y1) of the transformed vectors. The frequency error is obtained as being equal to the angular derivative of the average vector.
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公开(公告)号：DE69924055D1
公开(公告)日：2005-04-14
申请号：DE69924055
申请日：1999-07-20
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
IPC: H04L27/00 , H04L27/22 , H04L27/227
Abstract: The process uses multiplication of vector angle and analysis of derivative to locate error. The procedure provides an estimation of the frequency error of a demodulator which is used to reconstruct two binary signals (I,Q) carried on two carriers of the same frequency but operating in phase quadrature. The procedure comprises the first stage of forming vectors having the successive pairs of values (I,Q) of two binary signals as components. The second stage includes applying to each vector a transformation which multiplies its angle by four, at least when it is equal to a multiple of /4, whilst retaining its modulus. The third stage includes calculating the average (x1,y1) of the transformed vectors. The frequency error is obtained as being equal to the angular derivative of the average vector.
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公开(公告)号：FR2790344A1
公开(公告)日：2000-09-01
申请号：FR9902653
申请日：1999-02-26
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
Abstract: The invention concerns a COFDM demodulator comprising a fast Fourier transform circuit (14) analysing a signal received in a window corresponding to a symbol, each symbol carrying several phase and amplitude modulated carriers, whereof some (P), frequency-shifted in a predetermined manner from one symbol to the next, are set up as pilots; a two-dimensional filter (18) for interpolating, from anchors (A) corresponding to the pilots as they are received from several consecutive symbols (S), the distortion whereto each carrier is subjected, and means (12) for correcting the window offset relatively to an optimal position. The demodulator comprises means (42) for correcting each distortion on the basis of the widow offset corrections produced respectively for the symbol associated with the distortion and for the symbols associated with the anchors interpolating the distortion.
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29.发明专利
公开(公告)号：FR2877787A1
公开(公告)日：2006-05-12
申请号：FR0452576
申请日：2004-11-09
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
Abstract: L'invention concerne un dispositif (28) de fourniture d'un signal numérique d'erreur (Errn), pour une boucle de correction de cadence d'un démodulateur numérique pour transmission numérique par modulation de phase, le module recevant successivement des paires de signaux numériques (In, Qn) représentatifs des composantes de signaux complexes, et comprenant un moyen de fourniture d'un signal de différence représentatif de la différence entre le module du signal complexe correspondant à la dernière paire de signaux numériques reçue et le module du signal complexe correspondant à la paire de signaux numériques précédemment reçue ; un moyen de fourniture d'un facteur de pondération qui dépend de l'angle entre le signal complexe correspondant à la dernière paire de signaux numériques reçue et le signal complexe correspondant à la paire de signaux numériques précédemment reçue ; et un moyen de fourniture du signal d'erreur proportionnel au produit du signal de différence et du facteur de pondération.
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公开(公告)号：DE69528796T2
公开(公告)日：2003-09-18
申请号：DE69528796
申请日：1995-06-21
Applicant: ST MICROELECTRONICS SA
Inventor： MEYER JACQUES
Abstract: Two registers and counters are set up. The first having a register R and register Lambda with a counter dR. The second has a register Q and register U with a second counter dQ. The polynomial coefficients to be tested are stored in descending order, with the counter dQ initialised to 2t-1 and counter dR to 2t. (2t-1) steps are carried out and 1) If the counter contents are equal, and the register R is null a set of mathematical transforms are carried out, with the counters decremented. 2) If the counter contents in counter dR are smaller than dQ, then the counter contents are exchanged, and the mathematical transforms carried out as before. At the end of the process, the errors are found in the registers.
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