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    DUPLEX TRANSMISSION METHOD FOR ELECTROMAGNETIC TRANSPONDER SYSTEM
    21.
    发明专利
    DUPLEX TRANSMISSION METHOD FOR ELECTROMAGNETIC TRANSPONDER SYSTEM 失效

    公开(公告)号：JP2000332647A

    公开(公告)日：2000-11-30

    申请号：JP2000104892

    申请日：2000-04-06

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART LUC ,  BARDOUILLET MICHEL ,  ENGUENT JEAN-PIERRE

    IPC: G06K19/07 ,  G06K7/00 ,  G06K17/00 ,  H04B1/59 ,  H04B5/02

    Abstract: PROBLEM TO BE SOLVED: To provide a method for duplex transmission between a terminal and a transponder in an electromagnetic transponder system. SOLUTION: Each of the terminal 40 and the transponder 10 is provided with an oscillation circuit 24, a modulation means and a demodulation means, the amplitude modulation transmission of a signal to be transmitted from the terminal 40 to the transponder 10 and the transmission of a signal from the transponder 10 to the terminal 40 and suited so as to follow the phase demodulation of the terminal 40 are simultaneously executed and an amplitude modulation rate is

    27.
    发明专利
    未知

    公开(公告)号：DE60315399D1

    公开(公告)日：2007-09-20

    申请号：DE60315399

    申请日：2003-10-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART LUC

    IPC: G11C17/16 ,  G01C22/02 ,  G11C7/06

    Abstract: The monotonic counter is implemented as an integrated circuit where each counting bit (B1,B2,B3,B4) is provided by a memory cell (11) containing at least one memory element constituted of a resistor of polycrystalline silicon which is programmable by an irreversible decrease of its resistance. The counter also comprises a circuit (30) for decoding the states of memory cells for obtaining the resultant count. The programming of the resistor of polycrystalline silicon is by a temporary passage of a constraint current which is higher than a current for which the resistance has the maximum value. Each counting cell comprises a programming resistor connected between a first supply terminal and a differential read terminal, and at least one programming interrupter connecting the read terminal to a second supply terminal. The programming resistor is in the form of two resistors of polycrystalline silicon which are identical in size and doping level. The counter also comprises a circuit for programming control (CTRL) of each counting cell and for providing control signals to each programming interrupter. The four bits (B1,B2,B3,B4) are arranged in a line of cells (11) which are all read simultaneously for obtaining the outputs (S1,S2,S3,S4). The number of cells in the state 0 and the state 1 is detected by the decoding circuit (30) which has five counting outputs (C0,C1,C2,C3,C4) linked to the four inputs by a NAND gate (31), nine AND gates (32,33,34,35,36,37,38,39,40), two OR gates (41,42), and a NOR gate (43).

    VERROUILLAGE D'UN CIRCUIT INTEGRE
    28.
    发明专利
    VERROUILLAGE D'UN CIRCUIT INTEGRE 未知

    公开(公告)号：FR2875949A1

    公开(公告)日：2006-03-31

    申请号：FR0452183

    申请日：2004-09-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： WUIDART LUC ,  MARINET FABRICE

    IPC: H01L23/58 ,  G11C7/24 ,  H01L27/02

    Abstract: L'invention concerne la protection d'un circuit intégré en conditionnant le démarrage de tout ou partie du circuit à la présence d'une clé (KEY), enregistrée de façon non volatile dans le circuit postérieurement à sa fabrication et dépendant d'au moins un premier paramètre (A, ID) présent de façon non volatile dans le circuit à l'issue de sa fabrication.

    30.
    发明专利
    未知

    公开(公告)号：DE60201023T2

    公开(公告)日：2005-08-18

    申请号：DE60201023

    申请日：2002-04-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： BARDOUILLET MICHEL ,  WUIDART LUC

    IPC: G11C17/00 ,  G06K19/10 ,  G11C5/00 ,  G11C8/20 ,  H03K3/356 ,  H03K5/15

    Abstract: The invention concerns a circuit ( 1 ) for storing a binary code (B 1 , B 2 , Bi- 1 , Bi, Bn- 1 , Bn) in an integrated circuit chip, comprising an input terminal ( 2 ) applying a signal (E) triggering reading of the code, output terminals ( 31, 32, 3 i-1, 3 i, 3 n-1, 3 n) for delivering said binary code, first electrical paths (P 1 , P 2 , Pi, Pn) individually connecting said input terminal to each output terminal, each path inputting a fixed delay in the manufacture of the integrated circuit, and means ( 4, 51, 52, 5 i, 5 n) simultaneously integrating the binary states present in output of the electrical paths.

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