公开(公告)号：EP0986107A1

公开(公告)日：2000-03-15

申请号：EP98830523.1

申请日：1998-09-08

Applicant: STMicroelectronics S.r.l.

Inventor： Vajana, Bruno ,  Dalla Libera, Giovanna

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/115

Abstract: Cell array structure for an electrically erasable and programmable non-volatile memory device comprising an array of memory cells (1,2) arranged in rows (WL k ,WL k+1 ) and columns (BL i ,BL i+1 ) and grouped together in groups to form individually readable, programmable and erasable memory locations (BY1,BY2), each memory location having a respective control electrode (CGa,CGb) common to all the memory cells of the memory location. Conductor lines (100a,100b) directly contacting respective control electrodes of the memory locations are provided for externally selecting the control electrodes of the memory locations.

Abstract translation: 一种用于电可擦除和可编程的非易失性存储器件的电池阵列结构，包括排列成行（WLk，WLk + 1）和列（BLi，BLi + 1）的一组存储器单元（1,2） 形成单独可读，可编程和可擦除存储器位置（BY1，BY2），每个存储器位置具有对存储器位置的所有存储器单元共同的相应控制电极（CGa，CGb）。 提供与存储单元的各个控制电极直接接触的导体线（100a，100b），用于外部选择存储器位置的控制电极。

公开(公告)号：EP0975021A1

公开(公告)日：2000-01-26

申请号：EP98830444.0

申请日：1998-07-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Galbiati, Nadia ,  Dalla Libera, Giovanna ,  Vajana, Bruno

IPC: H01L21/8234 ,  H01L27/06

CPC classification number: H01L27/0629

Abstract: The manufacture process comprises the following steps in succession: depositing a gate oxide layer on a silicon substrate (2) defining a transistor area (5) and a resistor area (6); depositing a multicrystal silicon layer (11) on the gate oxide layer (10); removing selective portions of the multicrystal silicon layer (11) to form a gate region (11a) over the transistor area (5) and a protective region (11b) completely covering the resistor area (6); forming source and drain regions (22) in the transistor area (5), laterally to the gate region (11a); forming silicide regions (25, 26 and 27) on and in direct contact with the source and drain regions (22), the gate region (11a) and the protective region (11b); removing selective portions of the protective region (11b) to form a delimitation ring (34); and implanting ionic dopants in the resistor area (6), inside the area defined by the protective ring (34), to form a lightly doped resistor (38) which has no silicide regions directly on it.

Abstract translation: 制造过程包括以下步骤连续：在硅衬底上沉积栅极氧化物层（2）的晶体管限定区域（5）和一个电阻器区（6）; 沉积栅极氧化物层上的多晶硅层（11）（10）; 去除多晶硅层（11）的选择部分以在所述晶体管区（5）和保护区域（11B）的栅极区（11A）完全覆盖调用该电阻区域（6）; 在晶体管区域中形成源和漏区（22）（5），晚反弹到栅极区域（11A）; 上，并在与所述源和漏区（22），所述栅极区域（11a）和所述保护区（11b）的直接接触形成硅化物区（25，26和27）; 去除保护区域（11B）的选择部分，以形成一个环划界（34）; 和植入在电阻区（6）的离子掺杂剂，由保护环（34）所限定的区域内部，以形成轻度掺杂的电阻器（38），其具有直接在其上没有形成硅化物区。

公开(公告)号：EP2034518A3

公开(公告)日：2009-06-03

申请号：EP08021768.0

申请日：1998-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Galbiati, Nadia ,  Dalla Libera, Giovanna ,  Vajana, Bruno

IPC: H01L27/105 ,  H01L27/088 ,  H01L27/115 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247

CPC classification number: H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

Abstract: An integrated electronic device with a silicon substrate (1) having low-voltage regions (19) and high-voltage regions (13) therein.
Low-voltage transistors (70) are in the LV regions and high-voltage transistors (71) are in the HV regions.
The transistors are different in respect of the silicidation of source and drain regions.
Each LV transistor has silicided source, gate and drain (55,57a1,57a2) and each HV transistor has silicided gate (57d) and non-silicided source and drain regions (64).

Abstract translation: 用具有低电压的区域（19）和高压区（13）在其中的硅衬底（1）的集成电子器件。 低电压晶体管（70）是在LV区域和高电压晶体管（71）是在HV区域。 晶体管处于相对于源和漏区的硅化的不同。 每个晶体管具有LV硅化源极，栅极和漏极（55,57a1,57a2），并且每个晶体管HV已硅化栅极（57D）和非硅化源和漏区（64）。

公开(公告)号：EP0975020B1

公开(公告)日：2009-02-11

申请号：EP98120033.0

申请日：1998-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Galbiati, Nadia ,  Dalla Libera, Giovanna ,  Vajana, Bruno

IPC: H01L21/8234 ,  H01L21/8239 ,  H01L27/105

CPC classification number: H01L21/823418 ,  H01L21/823443 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

公开(公告)号：EP1058299A1

公开(公告)日：2000-12-06

申请号：EP99830347.3

申请日：1999-06-04

Applicant: STMicroelectronics S.r.l.

Inventor： Dalla Libera, Giovanna ,  Vajana, Bruno ,  Patelmo, Matteo

IPC: H01L21/28 ,  H01L29/788 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11546 ,  H01L29/42324

Abstract: The manufacturing process comprises the steps of: forming a first insulating region (25b) on top of an active area; forming a tunnel region (98) at the side of the first insulating region; depositing and defining a semiconductor material layer (27) using a floating gate mask (90). In this way, a floating gate region (95) is formed. The floating gate mask (90) has an opening (92) having an internal delimiting side (90b) extending at a preset distance from a corresponding outer delimiting side (90a) of the mask, so that the floating gate region (95) forms inner a hole (97), and the tunnel area (98) is defined, as regards its length, by the floating gate mask alone. The hole (97) is filled with a dielectric material layer (103). Then, the surface of the floating gate region is planarized, and an insulating region (101) of dielectric material is made. Then a control gate region (43b) and conductive regions (65a, 65b) in the active area (14) are formed.

Abstract translation: 制造过程包括以下步骤：形成在有源区之上的第一绝缘区域（25B）; 形成在所述第一绝缘区域的一侧上的隧道区域（98）; 沉积并使用浮动栅极掩模（90）定义的半导体材料层（27）。 以这种方式，浮置栅极区域（95）形成。 浮栅掩模（90）具有在具有开口（92）在内部限定侧（90b）的在预先设定的距离从掩模的对应的外界定侧（90A）延伸，所以没有浮置栅极区域（95）形式的内部 一个孔（97），以及隧道区域（98）被定义，作为单独关于其长度，由浮动栅极掩模。 所述孔（97）填充有介电材料层（103）。 然后，浮置栅极区域的表面被平坦化，并以绝缘介电材料的区域（101）制成。 然后控制栅极区域（43B）和导电区域（65A，65B）在有源区（14）形成。

公开(公告)号：EP1024527A2

公开(公告)日：2000-08-02

申请号：EP99126235.3

申请日：1999-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

IPC: H01L21/8246 ,  H01L21/8247

CPC classification number: H01L27/112 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/11293

Abstract: Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

Abstract translation: 提出了一种在双栅极EEPROM工艺流程中获得多级ROM的方法。 该方法开始于在半导体衬底上分别定义用于ROM单元的晶体管，电可擦除非易失性存储单元的晶体管和存储电路的附加晶体管的有源区。 然后，集成电容器集成在存储电路中。 根据该方法，在用于形成集成电容器的注入步骤期间，类似地植入ROM单元的至少一个有效区域。

公开(公告)号：EP1014441A1

公开(公告)日：2000-06-28

申请号：EP98830771.6

申请日：1998-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Vajana, Bruno ,  Dalla Libera, Giovanna ,  Cremonesi, Carlo ,  Galbiati, Nadia

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

Abstract: The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).

Abstract translation: 形成用于LV晶体管的源区和漏区（48'，55'）的步骤包括以下步骤：向LV栅区（43a）横向形成牺牲隔离物（101）; 以牺牲间隔物（101）自对准的方式形成LV源极和漏极区（55'）; 去除牺牲隔离物（101）; 形成HV晶体管的HV栅极区域（43d）; 形成选择晶体管的栅极区域（43c）; 形成存储晶体管的控制栅极区域（43b）; 同时形成与LV栅极区域（43a）自身对准的LDD区域（48'），与HV栅极区域（43d），源极和漏极区域（65a，65b）自身对准的HV源极和漏极区域（64） 与选择栅极区域（43c）和浮动栅极区域（27b）对准; 沉积介电层; 用保护硅化物掩模（72）覆盖HV和存储区域; 各向异性地蚀刻介电层，以在LV栅极区域（43a）的横向形成永久间隔物（52'）。 去除保护硅化物掩模（72）; 以及在LV源极和漏极区域（48'，55'）和LV栅极区域（43a）上形成硅化物区域（75a1,75a2）。

公开(公告)号：EP0996162A1

公开(公告)日：2000-04-26

申请号：EP98830628.8

申请日：1998-10-21

Applicant: STMicroelectronics S.r.l.

Inventor： Dalla Libera, Giovanna ,  Vajana, Bruno

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Semiconductor memory device, comprising at least one memory cells row, each memory cell comprising an information storing element (2) and a related select transistor (1) for selecting the storing element (2). The select transistor (1) comprises a gate oxide region (11) over a silicon substrate (14), a lower polysilicon layer (10) and an upper polysilicon layer (6) superimposed to the gate oxide region (11) and electrically insulated therebetween by an intermediate dielectric layer (9) interposed between them. The gate oxide regions (11) of the select transistors (1) of the at least one row are separated by field oxide regions (15), and the lower and upper polysilicon layers (10,6) and the intermediate dielectric layer (9) extend along the row over the gate oxide regions (11) of the select transistors (1) and over the field oxide regions (15). Along the row it is provided at least one opening in the upper polysilicon layer (6), intermediate dielectric layer (9) and lower polysilicon layer (10), inside of which a first contact element (20) suitable to electrically connect the lower and upper polysilicon layers (6,10) is inserted.

Abstract translation: 半导体存储器件，包括至少一个存储单元行，每个存储器单元包括信息存储元件（2）和用于选择存储元件（2）的相关选择晶体管（1）。 选择晶体管（1）包括在硅衬底（14）上的栅极氧化物区域（11），叠加到栅极氧化物区域（11）上的下部多晶硅层（10）和上部多晶硅层（6），并在其间电绝缘 通过介于它们之间的中间介电层（9）。 至少一行的选择晶体管（1）的栅极氧化物区域（11）由场氧化物区域（15）分离，并且下部和上部多晶硅层（10,6）和中间电介质层（9） 沿着选择晶体管（1）的栅极氧化物区域（11）上的行并且在场氧化物区域（15）上延伸。 沿着排，它设置在上多晶硅层（6），中间介电层（9）和下多晶硅层（10）中的至少一个开口，其中第一接触元件（20）适于将下部和 上部多晶硅层（6,10）被插入。

公开(公告)号：EP0994513A1

公开(公告)日：2000-04-19

申请号：EP98830614.8

申请日：1998-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia, c/o STMicroelectronics S.r.l. ,  Vajana, Bruno

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: The invention relates to a simplified non-DPCC process for the definition of the tunnel area in non-volatile memory cells with semi-conductor floating gate, which are non-aligned and incorporated in a matrix of cells with associated control circuitry, to each cell a selection transistor being associated, the process comprising at least the following phases:

growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells;
tunnel mask for defining the area of tunnel;
cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semi-conductor;
growth of tunnel oxide;

Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

Abstract translation: 本发明涉及一种用于在非易失性存储器单元具有半导体浮动栅极，其是未对齐，并与相关的控制电路单元的矩阵掺入的隧道区域的定义简化的非DPCC过程中，给每个小区 一选择晶体管被关联，所述方法包括至少以下阶段：所述感测晶体管和所述单元的栅极的电介质层的生长或沉积; 隧道限定用于隧道的区域掩模; 清洁栅极介电层的蚀刻在隧道到半导体的表面的面积; 隧道氧化物的生长; 有利地，隧道掩模通过选择晶体管所占据的区域上方延伸。

公开(公告)号：EP0977265A1

公开(公告)日：2000-02-02

申请号：EP98830461.4

申请日：1998-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Dalla Libera, Giovanna ,  Pio, Federico

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L27/088 ,  H01L21/823475

Abstract: A circuit structure integrated in a semiconductor substrate (40) comprises at least one pair of transistors (20,21) being formed each in a respective active area region (30) and having a source region (22) and a drain region (23), as well as a channel region (24) intervening between the source and drain regions (22,23) and being overlaid by a gate region (25); the gate regions (25) are connected electrically together by an overlying conductive layer (28) and respective contacts (14) wherein the contacts (14) between the gate regions (24) and the conductive layer (28) are formed above the active areas (30).

Abstract translation: 集成在半导体衬底（40）中的电路结构包括至少一对晶体管（20,21），每个晶体管分别形成在相应的有源区域（30）中并且具有源极区（22）和漏极区（23） ，以及介于源区和漏区（22,23）之间并被栅极区域（25）覆盖的沟道区（24）; 栅极区域（25）通过覆盖的导电层（28）和相应的触点（14）电连接在一起，其中栅极区域（24）和导电层（28）之间的触点（14）形成在有源区域 （30）。