Conversion of a numeric command value in a constant frequency PWM drive signal for an electromagnetic load
    24.
    发明公开
    Conversion of a numeric command value in a constant frequency PWM drive signal for an electromagnetic load 有权
    在脉冲宽度调制驱动信号具有恒定频率转换一个数字命令值用于电磁负载

    公开(公告)号:EP1014552A1

    公开(公告)日:2000-06-28

    申请号:EP98830775.7

    申请日:1998-12-23

    CPC classification number: G06F1/025 H02M7/53873

    Abstract: In driving a load in a PWM mode in function of numeric command values of a certain N number of bits by converting the current numeric command value in at least a driving PWM signal (PWM_A, PWM_B) having a fixed frequency and a duty cycle proportional to the numeric command value, comparing through a comparator (COMPARATOR) the N bit numeric value with the counter of an up/down counter of the same number (N) of bits (N BIT UP/DOWN COUNTER) functioning in a continuous mode at the frequency of a system's clock signal (SysClk), the definition of the conversion may be enhanced withtout correspondingly increasing the number of bits of the UP/DOWN COUNTER. This is achieved by incrementing by more than a unit (N+3) the number of bits on which a certain command value is mapped; converting the N most significant bits with the exception of said additional bits of said command value by means of said comparator and up/down counter; decoding said additional bits by generating a corresponding plurality of intermediate levels of variation of the duty cycle, each of which has a duration of half a clock period (SysClk/2) producing a plurality of signals, outphased among each other by half a clock period (A, B, C, D, B, A', B', C', D', E'); generating said driving PWM signal (IN_A, IN_B) by multiplating (MULTIPLEXER) said signals outphased among each other by half a clock period, carrying out logic combinations of such signals in function of the most significative bit (MSB) of the numeric command value and of said least significative additional bits.

    Abstract translation: 在通过在至少一个驱动PWM信号(PWM_A,PWM_B)将当前的数字指令值具有固定频率和占空比正比于驱动在比特的某些N个数字指令值的函数的PWM模式下的负载 数字指令值,通过比较器进行比较(比较器)的n个位数值与比特的相同数量(N)的上/下计数器的计数器(N位向上/向下计数器)中在连续方式工作的 一个系统的时钟信号(SYSCLK)的频率,所述转换的定义可能withtout相应增加UP / DOWN计数器的位的数目来增强。 这是通过多于一个单元(N + 3),其上的某命令值被映射的比特的数量递增实现; 由所述比较装置和上/下计数器,所述命令值的所述附加比特的异常转换的N个最显著比特; 解码由所述生成的占空比的变化中间电平的相应的多个附加位,每一个均具有半个时钟周期的持续时间(SYSCLK / 2)由半个时钟周期生产的信号的多个,海誓山盟之间Outphased (A,B,C,D,B,A 'B',C 'D',E“); 通过multiplating(多路复用器)生成所述驱动PWM信号(IN_A,IN_B)由所述半个时钟脉冲周期中海誓山盟信号Outphased,在数字指令值的最有意义的位(MSB)的函数来进行搜索信号的逻辑组合和 说,至少有意义的附加位。

    A method of PWM driving a brushless motor with digitally stored voltage profiles with reduced losses
    25.
    发明公开
    A method of PWM driving a brushless motor with digitally stored voltage profiles with reduced losses 失效
    与数字存储的电压分布和降低损失的无刷电动机的PWM驱动的方法

    公开(公告)号:EP0955721A1

    公开(公告)日:1999-11-10

    申请号:EP98830270.9

    申请日:1998-05-05

    CPC classification number: H02P6/14 H02P6/085

    Abstract: A method of driving a multiphase brushless motor with N star-connected windings wherein all the N windings are driven according to a certain predefined periodic voltage profile intended as the differential voltage between the winding's terminal and the star center, includes cyclically keeping for a certain time interval one of the N windings in a fixed state of low or high saturation by applying to the other N-1 phase windings instantaneous voltages according to a profile such that the modulated voltage of the star center subtracted or added to the low or high saturation voltage applied to the terminal of said one winding produce a resultant voltage on the winding of a value coherent with said predefined voltage profile.
    The number of intervals, in an entire electric period, in which said fixed high or low saturation state of one winding is produced, depends on the predefined driving profile and upon the number N of windings of the motor.

    Abstract translation: 驱动具有worin所有的N个绕组被驱动雅丁于预期作为绕组的端子和星形中心之间的差分电压在某一预定周期电压属性N星形连接绕组的多相无刷电动机的方法,包括循环地保持一定时间 通过向其他N-1相绕组瞬时电压雅丁到配置文件搜索在低或高饱和度的固定状态的N个绕组的间隔一个做星形中心消减的调制电压或加入到低或高饱和电压 施加到所述一个绕组上产生相干与所述预定义的电压分布的值的卷绕所得的电压的端子。 间隔的中到整个电动周期的数目,其中,所述固定一个绕组中产生的高或低的饱​​和状态,依赖于预定义的驾驶概况并且在电动机的绕组的数目N.

    Driving apparatus for an electromagnetic load and related method
    26.
    发明公开
    Driving apparatus for an electromagnetic load and related method 审中-公开
    最新和最新的Verfahren

    公开(公告)号:EP2306631A1

    公开(公告)日:2011-04-06

    申请号:EP10178995.6

    申请日:2010-09-23

    Inventor: Galbiati, Ezio

    CPC classification number: H02P6/001 H02P6/085 H02P6/14 H02P6/34

    Abstract: There is described a driving apparatus for an electromagnetic load (10), said apparatus comprises at least one pair of first (M4) and second (M5) transistors both arranged so as to form a current path with the electromagnetic load for discharging the current (Im) produced by the electromagnetic load. The first transistor (M4) comprises an inherent diode (D4) between the non-drivable terminals and the apparatus comprises means (120) to control the switching on and off of said at least one pair of first and second transistors, means (100) adapted to allow the second transistor (M5) to be diode connected, with said first (M4) switched off and said second transistor (M5) deactivated, so that the current (Im) produced by said electromagnetic load, crossing said inherent diode, creates an overvoltage between the terminals of the second diode-configured transistor such to exceed the conduction threshold voltage (Vt) thereof.

    Abstract translation: 描述了一种用于电磁负载(10)的驱动装置,所述装置包括至少一对第一(M4)和第二(M5)晶体管,其被布置成与用于放电电流的电磁负载形成电流路径 Im)由电磁负载产生。 第一晶体管(M4)包括在不可驱动端子之间的固有二极管(D4),并且该装置包括用于控制所述至少一对第一和第二晶体管的导通和关断的装置(120),装置(100) 适于允许所述第二晶体管(M5)被二极管连接,所述第一(M4)关断和所述第二晶体管(M5)停用,使得由所述电磁负载产生的与所述固有二极管交叉的电流(Im)产生 第二二极管配置晶体管的端子之间的过电压超过其导通阈值电压(Vt)。

    ">
    30.
    发明公开
    "Driving circuit and method for preventing voltage surges on supply lines while driving a dc motor" 有权
    用于防止电压驱动器电路和方法的DC马达的操作期间在供给线浪涌

    公开(公告)号:EP1258980A3

    公开(公告)日:2004-02-04

    申请号:EP01203450.0

    申请日:2001-09-12

    CPC classification number: H02P6/24

    Abstract: A driving circuit of a DC motor comprises a control circuit producing a control signal, a motor drive circuit, commanded by the control circuit, producing respective command signals for the switches of an output power stage driving the windings of the motor connected to supply lines in parallel to a filter capacitor. The driving circuit prevents generation of voltage surges of significant magnitude on the supply lines because the driving circuit has logic circuits preventing any substantial inversion of direction of flow of the current in the supply lines whenever the motor behaves as a current generator. The driving circuit implements a method of preventing generation of voltage surges on the supply lines of a DC motor comprising monitoring and comparing with a respective threshold at least a working parameter of the motor belonging to the group composed of: the voltage on the supply node of an output power stage of the motor, the voltage on at least a winding of the motor, the direction of flow of the current in the supply lines of the output power stage and the phase difference between the current circulating in at least a winding of the motor and the back electromotive force induced on the same winding; whenever at least one of the monitored parameters exceeds its respective threshold, forcing on each winding of the motor a voltage such to prevent substantial inversion of the direction of flow of the current on the supply lines.

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