中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.119 seconds)

    Integrated electronic circuit including non-linear devices
    3.
    发明公开
    Integrated electronic circuit including non-linear devices 有权
    Elektronische integrierte Schaltung mit nichtlinearen Vorrichtungen

    公开(公告)号：EP1289140A1

    公开(公告)日：2003-03-05

    申请号：EP01830536.7

    申请日：2001-08-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Zuffada, Maurizio ,  Betti, Giorgio ,  Chrappan Soldavini, Francesco

    IPC: H03H11/48

    CPC classification number: H03H11/481

    Abstract: The invention relates to a non-linear electronic device and, more particularly, to a non-linear capacitor.
    More specifically, but not exclusively, the invention relates to an electronic circuit device that may be integrated on a semiconductor substrate. Advantageously, the non-linear device is a capacitor formed by a feedback loop of cascade connected active blocks (2, 5, 6). Moreover, the invention may be integrated or used in association with a circuit network including other non-linear devices.

    Abstract translation: 本发明涉及非线性电子设备，更具体地，涉及一种非线性电容器。 更具体地但不排他地，本发明涉及可集成在半导体衬底上的电子电路器件。 有利地，非线性装置是由级联连接的有源块（2,5,6）的反馈回路形成的电容器。 此外，本发明可以与包括其他非线性设备的电路网络相关联或使用。

    Conversion of a numeric command value in a constant frequency PWM drive signal for an electromagnetic load
    5.
    发明公开
    Conversion of a numeric command value in a constant frequency PWM drive signal for an electromagnetic load 有权
    在脉冲宽度调制驱动信号具有恒定频率转换一个数字命令值用于电磁负载

    公开(公告)号：EP1014552A1

    公开(公告)日：2000-06-28

    申请号：EP98830775.7

    申请日：1998-12-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Galbiati, Ezio ,  Papillo, Lorenzo ,  Chrappan Soldavini, Francesco

    IPC: H02M7/5387

    CPC classification number: G06F1/025 ,  H02M7/53873

    Abstract: In driving a load in a PWM mode in function of numeric command values of a certain N number of bits by converting the current numeric command value in at least a driving PWM signal (PWM_A, PWM_B) having a fixed frequency and a duty cycle proportional to the numeric command value, comparing through a comparator (COMPARATOR) the N bit numeric value with the counter of an up/down counter of the same number (N) of bits (N BIT UP/DOWN COUNTER) functioning in a continuous mode at the frequency of a system's clock signal (SysClk), the definition of the conversion may be enhanced withtout correspondingly increasing the number of bits of the UP/DOWN COUNTER. This is achieved by incrementing by more than a unit (N+3) the number of bits on which a certain command value is mapped; converting the N most significant bits with the exception of said additional bits of said command value by means of said comparator and up/down counter; decoding said additional bits by generating a corresponding plurality of intermediate levels of variation of the duty cycle, each of which has a duration of half a clock period (SysClk/2) producing a plurality of signals, outphased among each other by half a clock period (A, B, C, D, B, A', B', C', D', E'); generating said driving PWM signal (IN_A, IN_B) by multiplating (MULTIPLEXER) said signals outphased among each other by half a clock period, carrying out logic combinations of such signals in function of the most significative bit (MSB) of the numeric command value and of said least significative additional bits.

    Abstract translation: 在通过在至少一个驱动PWM信号（PWM_A，PWM_B）将当前的数字指令值具有固定频率和占空比正比于驱动在比特的某些N个数字指令值的函数的PWM模式下的负载 数字指令值，通过比较器进行比较（比较器）的n个位数值与比特的相同数量（N）的上/下计数器的计数器（N位向上/向下计数器）中在连续方式工作的 一个系统的时钟信号（SYSCLK）的频率，所述转换的定义可能withtout相应增加UP / DOWN计数器的位的数目来增强。 这是通过多于一个单元（N + 3），其上的某命令值被映射的比特的数量递增实现; 由所述比较装置和上/下计数器，所述命令值的所述附加比特的异常转换的N个最显著比特; 解码由所述生成的占空比的变化中间电平的相应的多个附加位，每一个均具有半个时钟周期的持续时间（SYSCLK / 2）由半个时钟周期生产的信号的多个，海誓山盟之间Outphased （A，B，C，D，B，A 'B'，C 'D'，E“）; 通过multiplating（多路复用器）生成所述驱动PWM信号（IN_A，IN_B）由所述半个时钟脉冲周期中海誓山盟信号Outphased，在数字指令值的最有意义的位（MSB）的函数来进行搜索信号的逻辑组合和 说，至少有意义的附加位。

Patent Agency Ranking