公开(公告)号：EP0926687A1

公开(公告)日：1999-06-30

申请号：EP97830693.4

申请日：1997-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Olivo, Marco

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/106 ,  G11C29/52 ,  G11C29/76

Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps:

* repeating the sequential reading per bytes and parity check;
* verifying the consistency of the parity value with the value stored in the respective parity bit;
* if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

Abstract translation: 由由阵列或矩阵的单元（位）构成的闪存的损耗电荷的自检和校正错误的方法，其由行和列组织，可由矩阵分割的整个扇区可擦除和编程， 通过为每个存储器扇区实现至少一个附加行和至少一个附加列的单元来实现; 存储奇偶校验码是附加行和列，并且周期性地执行自检程序和最终校正程序，其由以下步骤组成：重复每字节的顺序读取和奇偶校验; 验证奇偶校验值与存储在相应奇偶校验位中的值的一致性; 如果验证是否定的，保留当前的行地址并继续从第一列开始顺序验证列奇偶校验，直到识别验证产生否定结果的列，并且如果如此个性化的故障位为“1”，则重新编程为 “0”。

公开(公告)号：EP0661714B1

公开(公告)日：1999-06-23

申请号：EP93830540.6

申请日：1993-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Olivo, Marco ,  Padoan, Silvia

IPC: G11C16/06

CPC classification number: G11C16/30