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    Electrically erasable and programable non-volatile memory cell
    1.
    发明公开
    Electrically erasable and programable non-volatile memory cell 审中-公开
    Elektrischlösch-und programmierbare nichtflüchtigeSpeicherzelle

    公开(公告)号：EP1376698A1

    公开(公告)日：2004-01-02

    申请号：EP02425416.1

    申请日：2002-06-25

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cappelletti, Paolo ,  Ghezzi, Paolo ,  Maurelli, Alfonso ,  Vendrame, Loris ,  Zabberoni, Paola

    IPC: H01L27/115 ,  G11C16/04

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

    Abstract: An electrically erasable and programmable non-volatile memory cell (205) integrated in a chip of semiconductor material (300) is proposed. The memory cell includes a floating gate MOS transistor (210m) having a source region (335) and a drain region (325) formed in a first well (315), a channel (340) being defined between the drain region and the source region during operation of the memory cell, a control gate region (350), and a floating gate (355) extending over the channel and the control gate region, and a bipolar transistor (215) for injecting an electric charge into the floating gate, the bipolar transistor having an emitter region (365) formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel, wherein the memory cell further includes a second well (320) insulated from the first well, the control gate region being formed in the second well.

    Abstract translation: 提出了集成在半导体材料（300）的芯片中的电可擦除和可编程的非易失性存储单元（205）。 存储单元包括具有形成在第一阱（315）中的源极区（335）和漏极区（325）的浮置栅极MOS晶体管（210m），在漏极区域和源极区域之间限定沟道（340） 在所述存储单元的操作期间，在所述通道和所述控制栅极区域上延伸的控制栅极区域（350）和浮置栅极（355）以及用于将电荷注入所述浮动栅极的双极晶体管（215） 双极晶体管，其具有形成在第一阱中的发射极区域（365），由第一阱构成的基极区域和由沟道组成的集电极区域，其中存储单元还包括与第一阱绝缘的第二阱（320） ，所述控制栅极区域形成在所述第二阱中。

    Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method
    2.
    发明公开
    Test structure for the measurement of contact to gate distance in non-volatile memory devices and corresponding test method 有权
    用于测量在非易失性存储器的非接触式门距离测试结构和相关联的测试程序

    公开(公告)号：EP1367597A1

    公开(公告)日：2003-12-03

    申请号：EP02425360.1

    申请日：2002-05-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Ghilardi, Tecla ,  Sali, Mauro ,  Servalli, Giorgio

    IPC: G11C29/00

    CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

    Abstract: The present invention relates to an improved integrated non-volatile memory device including a matrix of cells organised into rows, or word lines, and columns, or bit lines, and including corresponding row and column decoding circuits as well as read, modify and erase circuits for reading and modifying data stored in the memory cells. Advantageously, the integrated memory device comprises test structure (2) including a smaller second matrix (3) of cells comprising couples of word lines (WL) each having a difference contact to gate distance.
    Each couple of word lines is gradually misaligned from each adjacent couple of word lines by a distance that is variable from couple to couple.
    This proposed structure allows monitoring with a large statistic one of the most critical technology parameter for FLASH reliability.

    Abstract translation: 本发明涉及改进的集成的非易失性存储器装置，其包括组织为行的细胞，或字线，和列，或位线，的一个矩阵和包括对应的行和列解码电路以及读，修改和擦除电路 用于读取和修改存储在所述存储器单元中的数据。 有利地，所述集成的存储器装置包括测试结构（2）包括包含细胞的字线（WL）每一个都具有差接触到栅极距离耦合的较小的第二矩阵（3）。 每一对字线被从每个相邻的一对字线的距离逐渐错开确实是从耦合到耦合变量。 此提议的结构允许具有大统计量技术FLASH可靠性的最关键参数之一的监测。

    Method of analysis of the quality of contacts and vias in multi-level metallisation fabrication processes of semiconductor devices, and corresponding test chip architecture
    5.
    发明公开
    Method of analysis of the quality of contacts and vias in multi-level metallisation fabrication processes of semiconductor devices, and corresponding test chip architecture 审中-公开
    用于与多层金属化触点和Viaverbindungen在半导体制造过程中的质量分析方法和相关联的测试芯片架构

    公开(公告)号：EP1480271A1

    公开(公告)日：2004-11-24

    申请号：EP03425336.9

    申请日：2003-05-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso

    IPC: H01L23/544 ,  G01R31/316

    CPC classification number: H01L22/34 ,  G01R31/2853 ,  G01R31/2884 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A test chip has been conceived to perform all the measurements needed to evaluate the performances of interconnects (in particular, to measure the statistical failure distribution, the electromigration, and the leakage current), and an algorithm has been developed to detect the via failure at any of the available n metal layers. The test chip consists basically of a ROM memory array. The vias to be measured are realized in the columns of the array. Vias (or contact) failures are detected by forcing a predetermined current through both an array column and a reference column. The required failure analysis is attained by comparing the resulting voltage drops.

    Abstract translation: 测试芯片已经设想来执行所有评估互连的性能（特别地，以测量统计故障分布，电迁移，和泄漏电流）所需的测量，并在算法已经被开发，以检测通过故障在 任何可用金属ñ层。 测试芯片的基本上是一个ROM存储器阵列的besteht。 所述通孔是在所述阵列的列进行测量实现。 通孔（或触点）故障是通过迫使电流流过预定的两个阵列列和一个参考列的检测。 所需的故障分析是通过比较所得到的电压降获得的。

    Non-volatile memory cell with a single level of polysilicon
    6.
    发明公开
    Non-volatile memory cell with a single level of polysilicon 审中-公开
    Festwertspeicherzelle mit einer Polysiliziumebene

    公开(公告)号：EP1091408A1

    公开(公告)日：2001-04-11

    申请号：EP99830628.6

    申请日：1999-10-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Zatelli, Nicola

    IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

    CPC classification number: H01L27/11521 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

    Abstract: The memory cell (101) is of the type with a single level of polysilicon, and comprises a sensing transistor (20) and a select transistor (21). The sensing transistor (20) comprises a control gate region (6) with a second type of conductivity, formed in a first region of active area (30) of a substrate (3) of semiconductor material, and a floating gate region (9) which extends transversely relative to the first region of active area (30). The control gate region (6) of the sensing transistor (20) is surrounded by a first well (103) with the first type of conductivity, and in turn is surrounded, below and laterally, by a second well (104) with the second type of conductivity, thus forming a triple well structure (142). A second triple well structure (140) can be formed in a second region of active area (31) adjacent to the first region of active area (30), and can accommodate conduction regions (4, 5, 12, 14, 15) of the sensing transistor and of the select transistor (21).

    Abstract translation: 存储单元（101）是具有单层多晶硅的类型，并且包括感测晶体管（20）和选择晶体管（21）。 感测晶体管（20）包括形成在半导体材料的衬底（3）的有源区域（30）的第一区域中的具有第二类型导电性的控制栅极区域（6）和浮动栅极区域（9） 其相对于有源区域（30）的第一区域横向延伸。 感测晶体管（20）的控制栅极区域（6）由具有第一类型导电性的第一阱（103）围绕，并且又由第二阱（104）包围，在第二阱（104）的下面和侧面，第二阱 导电类型，从而形成三重阱结构（142）。 可以在与有源区域（30）的第一区域相邻的有源区域（31）的第二区域中形成第二三阱结构（140），并且可以适应传导区域（4,5,12,14,15） 感测晶体管和选择晶体管（21）。

    Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof
    8.
    发明公开
    Self-test and correction of loss of charge errors in a flash memory, erasable and programmable by sectors thereof 失效
    西班牙语Sektorenlöschbarenund-programmierbaren Flashspeicher的Selbsttest und Korrektur von Ladungsverlustfehlern

    公开(公告)号：EP0926687A1

    公开(公告)日：1999-06-30

    申请号：EP97830693.4

    申请日：1997-12-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Olivo, Marco

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/1068 ,  G06F11/106 ,  G11C29/52 ,  G11C29/76

    Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps:

    * repeating the sequential reading per bytes and parity check;
    * verifying the consistency of the parity value with the value stored in the respective parity bit;
    * if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

    Abstract translation: 由由阵列或矩阵的单元（位）构成的闪存的损耗电荷的自检和校正错误的方法，其由行和列组织，可由矩阵分割的整个扇区可擦除和编程， 通过为每个存储器扇区实现至少一个附加行和至少一个附加列的单元来实现; 存储奇偶校验码是附加行和列，并且周期性地执行自检程序和最终校正程序，其由以下步骤组成：重复每字节的顺序读取和奇偶校验; 验证奇偶校验值与存储在相应奇偶校验位中的值的一致性; 如果验证是否定的，保留当前的行地址并继续从第一列开始顺序验证列奇偶校验，直到识别验证产生否定结果的列，并且如果如此个性化的故障位为“1”，则重新编程为 “0”。

    Controlled hot-electron writing method for non-volatile memory cells
    9.
    发明公开
    Controlled hot-electron writing method for non-volatile memory cells 失效
    Regisertes Heiss-Elektronen-Schreibverfahrenfürnicht-flüchtigeSpeicherzellen

    公开(公告)号：EP0908895A1

    公开(公告)日：1999-04-14

    申请号：EP97830504.3

    申请日：1997-10-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cappelletti, Paolo ,  Ricco', Bruno ,  Esseni, David

    IPC: G11C16/00 ,  G11C16/06

    CPC classification number: G11C16/10 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/12

    Abstract: In order to optimise writing of the cell, the latter is written in a condition of equilibrium between the injection current ( I g ) and the displacement current ( C pp V sl ). In this way, during writing, the voltage of the floating gate region ( V fl ) remains constant, as does the drain current and the rise in the threshold voltage. In particular, both for programming and for soft-writing after erasure, the substrate of the cell is biased at a negative voltage ( V sb ) with respect to the source region, and the control gate region of the cell receives a ramp voltage ( V cg ) with a selected predetermined inclination ( V sl ) satisfying an equilibrium condition ( V sl I g,sat /C pp ).

    Abstract translation: 为了优化电池的写入，后者写入注入电流（Ig）和位移电流（CppVsl）之间的平衡状态。 以这种方式，在写入期间，浮动栅极区域（Vfl）的电压保持恒定，漏极电流和阈值电压的上升也保持恒定。 特别地，对于擦除后的编程和软写入，单元的基板相对于源极区域被偏压为负电压（Vsb），并且单元的控制栅极区域接收斜坡电压（Vcg） 具有满足平衡条件（Vs1

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