公开(公告)号：EP1863089A1

公开(公告)日：2007-12-05

申请号：EP06425371.9

申请日：2006-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Piazza, Fausto ,  Vigiani, Carlo ,  Zabberoni, Paola

IPC: H01L27/105 ,  H01L27/02 ,  H01L21/8239 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11534

Abstract: A method is described for manufacturing electrically non active structures of an integrated electronic circuit (1) formed on a semiconductor substrate (7) comprising first electrically active structures (2) which comprise electric components provided with conductive elements (16) of a first height (H1) projecting from said semiconductor substrate (7) and second electrically active structures (3) which comprise electric components provided with conductive elements (20) of a second height (H2) projecting from said semiconductor substrate (7), said first height being different from said second height, the method comprising the steps of:
- introducing, into the integrated electronic circuit (1), electrically non active structures (4) to superficially uniform the integrated electronic circuit (1),
- identifying, between the electrically non active structures (4), a first group (5) of electrically non active structures which is formed by those electrically non active structures comprised in areas (5a) which substantially extend for a predetermined radius (R) around each electric component belonging to the second electrically active structures (3),
- identifying, between the electrically non active structures (4), a second group (6) of electrically non active structures comprising electrically non active structures not belonging to the first group (5) of electrically non active structures,
- forming the electrically non active structures belonging to the first group (5) of electrically non active structures with elements (20a) projecting from the substrate (7) having a height equal to the second height (H2),
- forming the electrically non active structures belonging to the second group (6) of electrically non active structures with elements (16a) projecting from the substrate (7) having a height equal to the first height (H1), the elements (16a, 20a) belonging to the first (5) and second group (6) of electrically non active structures being formed by means of respective photolithographic steps.

Abstract translation: 描述了一种用于制造形成在半导体衬底（7）上的集成电子电路（1）的非电活动结构的方法，所述电子电路包括第一电活性结构（2），所述第一电活性结构（2）包括设置有第一高度的导电元件（16） H1）和第二电活动结构（3），所述第二电活性结构（3）包括设置有从所述半导体衬底（7）突出的第二高度（H2）的导电元件（20）的电气部件，所述第一高度不同 从所述第二高度，所述方法包括以下步骤：将集成电子电路（1）引入电非活动结构（4）以使所述集成电子电路（1）表面均匀; - 识别所述电非活动 结构（4），由非电活性结构组成的第一组（5），由非电活性结构构成 围绕属于第二电活动结构（3）的每个电气部件围绕预定半径（R）延伸的区域（5a）， - 识别在电非活性结构（4）之间的电子非活性结构（4）的第二组（6） 非活性结构包括不属于电非活性结构的第一组（5）的非电活性结构， - 形成属于电非活性结构的第一组（5）的非电活性结构，其中元件（20a）从 所述衬底（7）具有等于所述第二高度（H2）的高度， - 形成属于所述第二组（6）的电非活性结构的电非活性结构，其中从所述衬底（7）突出的元件（16a） 属于第一高度（H1）的高度，属于非活性结构的第一组（5）和第二组（6）的元件（16a，20a）通过相应的ph形成 光刻步骤。

公开(公告)号：EP0926687B1

公开(公告)日：2005-03-02

申请号：EP97830693.4

申请日：1997-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Maurelli, Alfonso ,  Olivo, Marco

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/106 ,  G11C29/52 ,  G11C29/76

Abstract: A method of self-test and correction of errors due to a loss charge for a flash memory constituted by an array or matrix of cells (bits), organized in rows and columns, erasable and programmable by whole sectors in which the matrix is divided, implemented by realizing at least an additional row and at least an additional column of cells for each memory sector; storing parity codes is the additional row and column, and carrying out periodically a self-test routine and eventual correction routine composed of the following steps: repeating the sequential reading per bytes and parity check; verifying the consistency of the parity value with the value stored in the respective parity bit; if the verification is negative, retaining the current row address and proceeding to sequentially verify column parity starting from the first column until identifying the column for which the verification yields a negative result, and if the failed bit so individuated is "1" reprogramming it to "0".

公开(公告)号：EP1156524A1

公开(公告)日：2001-11-21

申请号：EP00201716.8

申请日：2000-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Maurelli, Alfonso

IPC: H01L21/8247 ,  H01L21/8239 ,  H01L27/105 ,  H01L21/8238

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11546

Abstract: A process for the integration in a semiconductor chip of an integrated circuit including a high-density integrated circuit components portion and a high-performance logic integrated circuit components portion, providing for: over a semiconductor substrate (1), insulatively placing a silicidated polysilicon layer (5,11), comprising a polysilicon layer (5) selectively doped in accordance to a conductivity type of at least the high-performance logic integrated circuit components, covered by a silicide layer (11); selectively covering the silicidated polysilicon layer (5,11) with a hard mask (12); defining gate structures for the high-density integrated circuit components and for the high-performance logic integrated circuit components using said hard mask (12), the gate structures comprising the silicidated polysilicon layer (5,11) covered with the hard mask (12); in a dielectric layer (19) formed over the chip, forming contact openings for electrically contacting the high-density integrated circuit components and the high-performance logic integrated circuit components, wherein at least the contact openings for electrically contacting the high-density integrated circuit components are formed in self-alignment with the gate structures thereof.

Abstract translation: 一种用于在一个集成电路，包括在部分的高密度集成电路组件和部分的高性能逻辑集成电路部件的一个半导体芯片的整合过程中，提供了：半导体衬底（1），绝缘地放置硅化多晶硅层 （5.11），其包括在雅舞蹈选择性掺杂的导电类型的至少高性能逻辑集成电路部件，通过硅化物层（11）覆盖的多晶硅层（5）; 选择性地覆盖有硬掩模（12）的硅化多晶硅层（5,11）; 栅极定义结构为高密度集成电路组件和用于高性能逻辑集成电路部件使用所述的硬掩模（12），所述栅极结构包括覆盖有硬掩模的硅化多晶硅层（5,11）（12） ; 在介电层（19）形成在所述芯片中，形成接触开口，用于电接触所述高密度集成电路元件和高性能逻辑集成电路部件，worin至少用于电接触高密度接触开口集成电路 部件形成为与它们的栅极结构自对准。

公开(公告)号：EP0820103B1

公开(公告)日：2002-10-02

申请号：EP96830398.2

申请日：1996-07-18

Applicant: STMicroelectronics S.r.l.

Inventor： Maurelli, Alfonso ,  Riva, Carlo

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/66825 ,  H01L29/7885

公开(公告)号：EP0893831A1

公开(公告)日：1999-01-27

申请号：EP97830384.0

申请日：1997-07-23

Applicant: STMicroelectronics S.r.l.

Inventor： Baldi, Livio ,  Ghezzi, Paolo ,  Maurelli, Alfonso

IPC: H01L29/92 ,  H01L27/08

CPC classification number: H01L28/60 ,  H01L27/0805 ,  H01L29/94

Abstract: A high voltage capacitor (1), integratable monolithically on a semiconductor substrate (7) which accommodates a field oxide region (2) overlaid by a first layer of polycrystalline silicon (Poly 1) isolated from a second layer of polycrystalline silicon (Poly 2) by an interpoly dielectric layer (6), comprises two elementary capacitors (C1,C2) having a first common conductive plate (3) which is formed in the first layer of polycrystalline silicon (Poly 1). Each of these elementary capacitors has a second conductive plate (4,5) formed in the second layer of polycrystalline silicon (Poly 2) above the first plate (3), and includes said interpoly dielectric layer (6) as an isolation dielectric between the two plates.

Abstract translation: 一种高电压电容器（1），其单片地集成在半导体衬底（7）上，该半导体衬底（7）容纳由第二多晶硅层（Poly 2）隔离的第一多晶硅层（Poly 1）所覆盖的场氧化物区域（2） 通过间隔电介质层（6），包括两个元件电容器（C1，C2），其具有形成在第一多晶硅层（Poly 1）中的第一公共导电板（3）。 这些元件电容器中的每一个具有形成在第一板（3）上方的多晶硅（Poly 2）的第二层中的第二导电板（4,5），并且包括作为隔离介电层之间的隔离介电层（6） 两块板。

公开(公告)号：EP1526568A1

公开(公告)日：2005-04-27

申请号：EP03425687.5

申请日：2003-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Camerlenghi, Emilio ,  Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Zabberoni, Paola

IPC: H01L21/8247 ,  H01L21/8234

CPC classification number: H01L27/11526 ,  H01L21/823468 ,  H01L23/3192 ,  H01L27/105 ,  H01L27/11536 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A sealing method for electronic devices such as flash memory cells (4) and CMOS transistors (5) formed on a common semiconductor substrate (1) comprising the steps of:

forming at least a first conductive layer (7,9) on a first portion of semiconductor substrate (1),
forming a second conductive layer (11) on a second portion of semiconductor substrate (1),
defining a first plurality of gate regions (4a) of the memory cells (4) in at least a first conductive layer (7),
forming a first sealing layer (14) on the whole semiconductor substrate (1) to seal the first plurality of gate regions (4a),
defining a second plurality of gate regions (5a) of the CMOS transistors (5) in the second conductive layer (11),
forming a second sealing layer (16) on the whole semiconductor substrate (1) to seal the second plurality of gate regions (5a).

Abstract translation: 用于密封形成在半导体衬底上的电子器件的方法包括：形成与半导体衬底的第一部分相邻的多个第一电子器件，其中每个第一电子器件包括包含从半导体衬底突出的至少一个第一导电层的第一区域。 邻近第一区域形成第一密封层，用于密封多个第一电子器件。 在第一密封层附近形成保护层。 蚀刻保护层以形成与第一区域的侧壁相邻的保护性间隔物。 该方法还包括在半导体衬底的第二部分附近形成多个第二电子器件，每个第二电子器件包括第二区域，该第二区域包括从半导体衬底突出的第二导电层。 第二密封层邻近第二区域形成，用于密封多个第二电子器件，并邻近第一密封层以密封多个第一电子器件。

公开(公告)号：EP1376698A1

公开(公告)日：2004-01-02

申请号：EP02425416.1

申请日：2002-06-25

Applicant: STMicroelectronics S.r.l.

Inventor： Cappelletti, Paolo ,  Ghezzi, Paolo ,  Maurelli, Alfonso ,  Vendrame, Loris ,  Zabberoni, Paola

IPC: H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/7885

Abstract: An electrically erasable and programmable non-volatile memory cell (205) integrated in a chip of semiconductor material (300) is proposed. The memory cell includes a floating gate MOS transistor (210m) having a source region (335) and a drain region (325) formed in a first well (315), a channel (340) being defined between the drain region and the source region during operation of the memory cell, a control gate region (350), and a floating gate (355) extending over the channel and the control gate region, and a bipolar transistor (215) for injecting an electric charge into the floating gate, the bipolar transistor having an emitter region (365) formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel, wherein the memory cell further includes a second well (320) insulated from the first well, the control gate region being formed in the second well.

Abstract translation: 提出了集成在半导体材料（300）的芯片中的电可擦除和可编程的非易失性存储单元（205）。 存储单元包括具有形成在第一阱（315）中的源极区（335）和漏极区（325）的浮置栅极MOS晶体管（210m），在漏极区域和源极区域之间限定沟道（340） 在所述存储单元的操作期间，在所述通道和所述控制栅极区域上延伸的控制栅极区域（350）和浮置栅极（355）以及用于将电荷注入所述浮动栅极的双极晶体管（215） 双极晶体管，其具有形成在第一阱中的发射极区域（365），由第一阱构成的基极区域和由沟道组成的集电极区域，其中存储单元还包括与第一阱绝缘的第二阱（320） ，所述控制栅极区域形成在所述第二阱中。

公开(公告)号：EP1043778A1

公开(公告)日：2000-10-11

申请号：EP99830194.9

申请日：1999-04-06

Applicant: STMicroelectronics S.r.l.

Inventor： Maurelli, Alfonso ,  Zabberoni, Paola

IPC: H01L29/423 ,  H01L29/08 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/4238 ,  H01L29/66477

Abstract: Method of fabrication of a no-field transistor with no extra process costs, providing for defining an active area for the transistor surrounded by a thick field oxide layer (3), insulatively placing a polysilicon gate electrode (40) across the active area to define source/drain regions (50) of the no-field transistor, providing an implant protection mask (60) over a boundary (2) between at least one of the source/drain regions and the field oxide layer, selectively implanting in said source/drain regions a relatively heavy dose of dopants to form relatively heavily doped source/drain regions and to simultaneously dope the polysilicon gate electrode, characterized in that said polysilicon gate electrode is formed with lateral wings (41) extending towards said at least one source/drain region, and in that said implant protection mask (60) extends over said lateral wings but not over the polysilicon gate (40).

Abstract translation: 制造没有额外处理成本的无场晶体管的方法，提供限定由厚场氧化物层（3）围绕的晶体管的有源区域，绝缘地将多晶硅栅电极（40）放置在有源区域上以限定 源极/漏极区域（50），在源极/漏极区域和场氧化物层之间的至少一个之间的边界（2）上提供注入保护掩模（60），选择性地植入所述源极/漏极区域（50） 漏极区域是相当大量的掺杂剂以形成相对重掺杂的源极/漏极区域并且同时掺杂多晶硅栅极电极，其特征在于，所述多晶硅栅电极形成有向所述至少一个源极/漏极延伸的侧翼（41） 并且所述植入物保护掩模（60）在所述侧翼上延伸，但不在多晶硅栅极（40）上方延伸。

公开(公告)号：EP0471131B1

公开(公告)日：1999-02-03

申请号：EP90830343.1

申请日：1990-07-24

Applicant: STMicroelectronics S.r.l.

Inventor： Maurelli, Alfonso ,  Riva, Carlo

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/28 ,  G11C16/04

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7883

公开(公告)号：EP1526568B1

公开(公告)日：2009-02-25

申请号：EP03425687.5

申请日：2003-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Camerlenghi, Emilio ,  Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Zabberoni, Paola

IPC: H01L21/8247 ,  H01L21/8234

CPC classification number: H01L27/11526 ,  H01L21/823468 ,  H01L23/3192 ,  H01L27/105 ,  H01L27/11536 ,  H01L2924/0002 ,  H01L2924/00