公开(公告)号：EP1024527A2

公开(公告)日：2000-08-02

申请号：EP99126235.3

申请日：1999-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

IPC: H01L21/8246 ,  H01L21/8247

CPC classification number: H01L27/112 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/11293

Abstract: Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

Abstract translation: 提出了一种在双栅极EEPROM工艺流程中获得多级ROM的方法。 该方法开始于在半导体衬底上分别定义用于ROM单元的晶体管，电可擦除非易失性存储单元的晶体管和存储电路的附加晶体管的有源区。 然后，集成电容器集成在存储电路中。 根据该方法，在用于形成集成电容器的注入步骤期间，类似地植入ROM单元的至少一个有效区域。

公开(公告)号：EP1014441A1

公开(公告)日：2000-06-28

申请号：EP98830771.6

申请日：1998-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Vajana, Bruno ,  Dalla Libera, Giovanna ,  Cremonesi, Carlo ,  Galbiati, Nadia

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L27/11526 ,  H01L27/11529 ,  H01L27/11546

Abstract: The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).

Abstract translation: 形成用于LV晶体管的源区和漏区（48'，55'）的步骤包括以下步骤：向LV栅区（43a）横向形成牺牲隔离物（101）; 以牺牲间隔物（101）自对准的方式形成LV源极和漏极区（55'）; 去除牺牲隔离物（101）; 形成HV晶体管的HV栅极区域（43d）; 形成选择晶体管的栅极区域（43c）; 形成存储晶体管的控制栅极区域（43b）; 同时形成与LV栅极区域（43a）自身对准的LDD区域（48'），与HV栅极区域（43d），源极和漏极区域（65a，65b）自身对准的HV源极和漏极区域（64） 与选择栅极区域（43c）和浮动栅极区域（27b）对准; 沉积介电层; 用保护硅化物掩模（72）覆盖HV和存储区域; 各向异性地蚀刻介电层，以在LV栅极区域（43a）的横向形成永久间隔物（52'）。 去除保护硅化物掩模（72）; 以及在LV源极和漏极区域（48'，55'）和LV栅极区域（43a）上形成硅化物区域（75a1,75a2）。

公开(公告)号：EP0994513A1

公开(公告)日：2000-04-19

申请号：EP98830614.8

申请日：1998-10-15

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia, c/o STMicroelectronics S.r.l. ,  Vajana, Bruno

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524

Abstract: The invention relates to a simplified non-DPCC process for the definition of the tunnel area in non-volatile memory cells with semi-conductor floating gate, which are non-aligned and incorporated in a matrix of cells with associated control circuitry, to each cell a selection transistor being associated, the process comprising at least the following phases:

growth or deposition of a dielectric layer of gate of the sensing transistor and of the cells;
tunnel mask for defining the area of tunnel;
cleaning etching of the dielectric layer of gate in the area of tunnel up to the surface of the semi-conductor;
growth of tunnel oxide;

Advantageously, the tunnel mask is extended above the region occupied by the selection transistor.

Abstract translation: 本发明涉及一种用于在非易失性存储器单元具有半导体浮动栅极，其是未对齐，并与相关的控制电路单元的矩阵掺入的隧道区域的定义简化的非DPCC过程中，给每个小区 一选择晶体管被关联，所述方法包括至少以下阶段：所述感测晶体管和所述单元的栅极的电介质层的生长或沉积; 隧道限定用于隧道的区域掩模; 清洁栅极介电层的蚀刻在隧道到半导体的表面的面积; 隧道氧化物的生长; 有利地，隧道掩模通过选择晶体管所占据的区域上方延伸。

公开(公告)号：EP0975022A1

公开(公告)日：2000-01-26

申请号：EP98120034.8

申请日：1998-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： Patelmo, Matteo ,  Dalla Libera, Giovanna ,  Galbiati, Nadia ,  Vajana, Bruno

IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546 ,  H01L29/42324

Abstract: The manufacturing method comprises, in sequence, the steps of: depositing an upper layer (43) of polycrystalline silicon; defining the upper layer, obtaining LV gate regions (43a) of low voltage transistors and undefined portions (43); forming LV source and drain regions (55) laterally to the LV gate regions; forming a layer of silicide (57a1, 57a2, 57) on the LV source and drain regions (55), on the LV gate regions (43a), and on the undefined portions (43); defining stack gate regions (43b, 43c) and HV gate regions (43d) of high-voltage transistors; and forming HV source and drain regions (64) and cell regions (65a, 65b).

Abstract translation: 所述制造方法包括，在顺序，下列步骤：多晶硅的上层（43）的存入; ，定义上层，获得低电压晶体管和未定义部分（43）的LV栅极区域（43A）; 形成LV源和漏区（55）尾盘反弹到LV栅极区; 形成硅化物上的LV栅极区域（43A）的LV源和漏区（55）的层（57a1，57a2，57）和上未定义部分（43）; 堆栈限定栅极区域（43B，43C）和高电压晶体管的栅极HV区（43D）; 以及形成HV源和漏区（64）和单元区域（65A，65B）。