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    High-voltage switch with low output ripple for non-volatile floating-gate memories
    21.
    发明公开
    High-voltage switch with low output ripple for non-volatile floating-gate memories 有权
    具有在输出一个低纹波用于非易失性浮栅存储器的高压开关

    公开(公告)号：EP1724784A1

    公开(公告)日：2006-11-22

    申请号：EP05425347.1

    申请日：2005-05-20

    Applicant: STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    Inventor： Ragone, Giancarlo ,  Crippa, Luca ,  Sangalli, Miriam ,  Micheloni, Rino

    IPC: G11C8/08 ,  G11C16/08 ,  H02M3/07 ,  H03K17/06

    CPC classification number: H02M3/073 ,  G11C5/145 ,  G11C8/08 ,  G11C16/08 ,  G11C16/12 ,  H02M2003/077 ,  H03K3/356104 ,  H03K17/063 ,  H03K17/6872 ,  H03K17/6874

    Abstract: A high-voltage switch (24) has a high-voltage input terminal (29), receiving a high voltage (HV), and an output terminal (31). A pass transistor (36), having a control terminal, is connected between the high-voltage input terminal (29) and the output terminal (31). The output of a voltage-multiplying circuit (40) of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit (40) is of a symmetrical type, has first and second charge-storage means (41, 42), receiving a clock signal (CK) of a periodic type, and has a first circuit branch (44, 48) and a second circuit branch (45, 49), which are symmetrical to one another and operate in phase opposition with respect to the clock signal (CK).

    Abstract translation: 的高电压开关（24）具有一个高电压输入端（29）接收高电压（HV），和输出端子（31）。 具有控制端子的导通晶体管（36），被连接在高电压输入端（29）和输出端子（31）之间。 电荷泵型的电压倍增电路（40）的输出被连接到控制终端。 电压倍增电路（40）是对称型，具有第一和第二电荷存储装置（41，42）接收周期性类型的时钟信号（CK），并具有第一电路支路（44，48 ）和第二电路支路（45，49），它们彼此对称和反相相对于所述时钟信号（CK）进行操作。

    Stabilisation method of the drain voltage in non-volatile multilevel memory cells and relating memory device
    26.
    发明公开
    Stabilisation method of the drain voltage in non-volatile multilevel memory cells and relating memory device 有权
    一种用于在非易失性存储器的稳定具有多状态存储器设备和相关联的漏极电压的方法

    公开(公告)号：EP1435623A1

    公开(公告)日：2004-07-07

    申请号：EP02425801.4

    申请日：2002-12-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Crippa, Luca ,  Ragone, Giancarlo

    IPC: G11C16/10

    CPC classification number: G11C16/12 ,  G11C11/5628

    Abstract: The present invention relates to a method and an electronic device for stabilising the voltage on the drain terminals of multilevel non volatile memory cells (3) in the programming step. In the method the application of said voltage is provided through a drain voltage regulator (2) having an output (OUT) connected to said terminals in a common circuit node (A) by means of a metal line (4) conduction path having a parasitic intrinsic resistance (R pars ). Advantageously, a feedback path (5) is provided between the node (A) and an input of the regulator (2).

    Abstract translation: 本发明涉及一种用于在电子稳定性伊辛上在编程步骤的多级非易失性存储器单元（3）的漏极端子处的电压的方法和设备。 在该方法中，所述电压的施加是通过在由金属线的方式共同的电路节点（A）连接到所述端子的漏极电压调节器（2），其具有在输出端（OUT）提供了具有寄生（4）导通路径 固有电阻（Rpars）。 有利地，所述节点（A）之间以及在调节器（2）的输入端提供的反馈路径（5）。

    Read circuit for a nonvolatile memory
    28.
    发明公开
    Read circuit for a nonvolatile memory 有权
    发言人LeseschaltungfüreinennichtflüchtigenSpeicher

    公开(公告)号：EP1071096A1

    公开(公告)日：2001-01-24

    申请号：EP99830469.5

    申请日：1999-07-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Crippa, Luca

    IPC: G11C16/28 ,  G11C7/06

    CPC classification number: G11C16/28

    Abstract: The read circuit (1') comprises an array branch (6) having an input array node (22) connected, via an array bit line (8), to an array cell (10); a reference branch (12) having an input reference node (32) connected, via a reference bit line (14), to a reference cell (16); a current-to-voltage converter (18) connected to an output array node (56) of the array branch (6) and to an output reference node (58) of the reference branch (12) to supply on the output array node (56) and the output reference node (58) the respective electric potentials (V M , V R ) correlated to the currents flowing in the array memory cell (10) and, respectively, in the reference memory cell (16); and a comparator (19) connected at input to the output array node (56) and output reference node (58) and supplying as output a signal (OUT) indicative of the contents stored in the array memory cell (10); and an array decoupling stage (80) arranged between the input array node (22) and the output array node (56) to decouple the electric potentials of the input and output array nodes (22, 56) from one another.

    Abstract translation: 读取电路（1'）包括具有通过阵列位线（8）连接到阵列单元（10）的输入阵列节点（22）的阵列分支（6）。 具有通过参考位线（14）连接到参考单元（16）的输入参考节点（32）的参考分支（12）; 连接到阵列分支（6）的输出阵列节点（56）和参考分支（12）的输出参考节点（58）的电流 - 电压转换器（18），以在输出阵列节点 56）和输出参考节点（58）分别与在阵列存储单元（10）中流动的电流和参考存储单元（16）相关的电位相关联的各个电位（VM，VR）; 以及比较器（19），其在输入端连接到输出阵列节点（56）和输出参考节点（58），并且作为输出提供指示存储在阵列存储单元（10）中的内容的信号（OUT）。 以及布置在所述输入阵列节点（22）和所述输出阵列节点（56）之间的阵列解耦级（80），以将所述输入和输出阵列节点（22,56）的电位彼此去耦。

    Voltage regulator for non-volatile memories implemented with low-voltage transistors
    30.
    发明公开
    Voltage regulator for non-volatile memories implemented with low-voltage transistors 有权
    SPANNUNGSREGLERFÜRNICHTFLÜCHTIGESPEICHEREINHEITEN MIT NIEDRIGSPANNUNGSTRANSISTOREN

    公开(公告)号：EP1892600A1

    公开(公告)日：2008-02-27

    申请号：EP06119456.9

    申请日：2006-08-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Crippa, Luca ,  Ragone, Giancarlo ,  Sangalli, Miriam ,  Campardo, Giovanni ,  Micheloni, Rino

    IPC: G05F1/56

    CPC classification number: G11C5/147 ,  G05F1/565 ,  G11C16/30

    Abstract: A voltage regulator (150I) integrated in a chip of semiconductor material is proposed. The regulator has a first input terminal for receiving a first voltage (Vhv) and an output terminal for providing a regulated voltage (Vreg) being obtained from the first voltage, the regulator including: a differential amplifier (205I) for receiving a comparison voltage (Vref) and a feedback signal (Vfb) being a function of the regulated voltage, and for proving a regulation signal (Vr) according to a comparison between the comparison voltage and the feedback signal, the differential amplifier having a first supply terminal being coupled with a reference terminal for receiving a reference voltage and a second supply terminal, a regulation transistor (MS) having a control terminal for receiving the regulation signal, and a conduction first terminal and a conduction second terminal being coupled through loading means (Rpup) between the reference terminal and the first input terminal of the regulator, the second terminal of the regulation transistor being coupled with the output terminal of the regulator, wherein the second supply terminal of the differential amplifier is coupled with a second input terminal of the regulator for receiving a second voltage (Vdd) being lower than the first voltage in absolute value, and wherein the regulator further includes a set of auxiliary transistors (MS1-MS5) being connected in series between the second terminal of the regulation transistor and the output terminal of the regulator, and control means (155) for controlling the auxiliary transistors according to the regulated voltage.

    Abstract translation: 提出了集成在半导体材料芯片中的电压调节器（150I）。 调节器具有用于接收第一电压（Vhv）的第一输入端子和用于提供从第一电压获得的调节电压（Vreg）的输出端子，所述调节器包括：差分放大器（205I），用于接收比较电压 Vref）和作为调节电压的函数的反馈信号（Vfb），并且根据比较电压和反馈信号之间的比较来证明调节信号（Vr），所述差分放大器具有与 用于接收参考电压的参考端子和第二供电端子，具有用于接收调节信号的控制端子的调节晶体管（MS），以及通过第二端子和第二端子之间的负载装置（Rpup）耦合的导通第一端子和导通第二端子 参考端子和调节器的第一输入端子，调节晶体管的第二端子与输出端子耦合 ，其中所述差分放大器的第二电源端与所述调节器的第二输入端耦合，用于接收低于绝对值中的所述第一电压的第二电压（Vdd），并且其中所述调节器还包括一组 辅助晶体管（MS1-MS5）串联连接在调节晶体管的第二端子和调节器的输出端子之间，以及控制装置（155），用于根据调节电压控制辅助晶体管。

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