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公开(公告)号：US20230309314A1
公开(公告)日：2023-09-28
申请号：US18108374
申请日：2023-02-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok Kim , Daewon Ha
CPC classification number: H10B51/20 , H10B51/10 , H01L29/516 , H01L29/78391
Abstract: A three-dimensional ferroelectric random access memory (3D FeRAM) device includes: a gate electrode extending in a vertical direction on a substrate; a ferroelectric pattern and a gate insulation pattern stacked on the gate electrode in a horizontal direction to surround the gate electrode; first and second channels spaced apart from each other in the horizontal direction on an outer sidewall of the gate insulation pattern; first source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the first channel; and second source/drain pattern structures spaced apart from each other in the vertical direction on an outer sidewall of the second channel.
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公开(公告)号：US20220199793A1
公开(公告)日：2022-06-23
申请号：US17443553
申请日：2021-07-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol KIM , Yongseok KIM , Ilgweon KIM , Seokhan PARK , Kyunghwan LEE , Jaeho HONG
IPC: H01L29/423 , H01L29/66 , H01L29/78 , H01L23/482
Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities
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公开(公告)号：US20220102352A1
公开(公告)日：2022-03-31
申请号：US17241860
申请日：2021-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kiseok LEE , Kyunghwan LEE , Dongoh KIM , Yongseok KIM , Hui-jung KIM , Min Hee CHO
IPC: H01L27/108
Abstract: A semiconductor memory device includes a bit line extending in a first direction, a channel pattern on the bit line, the channel pattern including first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions, first and second word lines provided on the horizontal portion and between the first and second vertical portions and extended in a second direction crossing the bit line, and a gate insulating pattern provided between the first word line and the channel pattern and between the second word line and the channel pattern.
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公开(公告)号：US20210359200A1
公开(公告)日：2021-11-18
申请号：US17110524
申请日：2020-12-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Yongseok KIM , Kohji KANAMORI , Unghwan PI , Hyuncheol KIM , Sungwon YOO , Jaeho HONG
Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.
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公开(公告)号：US20210049340A1
公开(公告)日：2021-02-18
申请号：US16806011
申请日：2020-03-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE , Daekwan Kim , Yohwan Noh
Abstract: An electronic device includes a substrate, a plurality of light sources, the plurality of light sources configured to emit an optical signal to an object through the substrate, at least one sensor underneath the substrate, the at least one sensor configured to detect biometric information associated with the object by receiving a reflected light signal, the reflected light signal corresponding to the optical signal reflected off the object and transferred through the substrate, and a multi-lens array including at least one support layer, a plurality of first lenses, and a plurality of second lenses, the at least one support layer in an upper portion of the at least one sensor, the plurality of first lenses on an upper surface of the at least one support layer, and the plurality of second lenses on a lower surface of the at least one support layer.
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Patent Agency Ranking
公开(公告)号：US20250113590A1
公开(公告)日：2025-04-03
申请号：US18976522
申请日：2024-12-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol KIM , Yongseok KIM , Huijung KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.
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公开(公告)号：US20240421613A1
公开(公告)日：2024-12-19
申请号：US18742518
申请日：2024-06-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE
IPC: H02J7/00
Abstract: An electronic device according to an embodiment may include: a battery, load, charging circuitry, and control circuitry. The charging circuitry may include a plurality of switches and be configured to, in a PPS mode, receive power adjusted in each specified charging period according to a charge amount of the battery from an external electronic device, convert a voltage of the received power based on a specified voltage conversion ratio using the plurality of switches, and supply the voltage-converted power to the battery and the load. The control circuitry may be configured to: control a gate voltage of at least one specified switch of the plurality of switches, based on a voltage of the battery being higher than a maximum allowed charging voltage or a current of the battery being higher than a maximum allowed charging current during the PPS mode.
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公开(公告)号：US20240322048A1
公开(公告)日：2024-09-26
申请号：US18606081
申请日：2024-03-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan LEE , Jeonil LEE , Minhee CHO , Daweon HA
IPC: H01L29/792 , H10B12/00
CPC classification number: H01L29/7926 , H10B12/482 , H10B12/485 , H10B12/488
Abstract: Provided is an integrated circuit device including a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction, disposed on the source line, and having a first sidewall and a second sidewall, a trapping layer on the first sidewall of the channel layer and including an oxide semiconductor, a word line on at least one sidewall of the trapping layer and extending in a second horizontal direction crossing the first horizontal direction, a gate insulation layer between the at least one sidewall of the trapping layer and the word line, and a bit line electrically connected to the channel layer and extending in the first horizontal direction, wherein the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.
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公开(公告)号：US20240191932A1
公开(公告)日：2024-06-13
申请号：US18583013
申请日：2024-02-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan LEE , Youngdeog KOH , Jihwan CHUN , Heecheol KANG , Kwangjoo KIM , Jinju KIM , Minkyung LEE
IPC: F25D23/00 , B23K26/359 , B41M5/00 , C23F1/36 , C25D11/04
CPC classification number: F25D23/00 , B41M5/0058 , C23F1/36 , C25D11/04 , B23K26/359 , F25D2323/06
Abstract: A manufacturing method of an aluminum exterior panel including preparing an aluminum material; machining to shape an edge of the aluminum material; implementing a fine multilayered pattern on a surface of the processed aluminum material; forming of forming fine corrugations on the surface of the aluminum material on which the fine multilayered pattern is implemented; anodizing to form pores on the surface of the aluminum material on which the fine corrugations are formed; digital printing of implementing a color and an image on the aluminum material on which the pores are formed; and sealing to close the pores.
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公开(公告)号：US20230389290A1
公开(公告)日：2023-11-30
申请号：US18200135
申请日：2023-05-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeonil LEE , Kyunghwan LEE , Min Hee CHO
CPC classification number: H10B12/315 , H10B12/482 , H10B12/485 , H10B53/10 , H10B53/30 , H01L29/0847
Abstract: A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.
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