High-Voltage Normally-Off Field Effect Transistor With Channel Having Multiple Adjacent Sections
    23.
    发明申请
    High-Voltage Normally-Off Field Effect Transistor With Channel Having Multiple Adjacent Sections 有权
    具有多个相邻截面的通道的高电压常关场效应晶体管

    公开(公告)号:US20160111497A1

    公开(公告)日:2016-04-21

    申请号:US14984408

    申请日:2015-12-30

    Abstract: A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel.

    Abstract translation: 提供具有多个电压阈值的通道的装置。 通道可以包括位于与作为常开通道的源电极相邻的第一部分和位于第一部分和作为常开通道的漏电极之间的第二部分。 该装置可以包括连接到源电极的电荷控制电极,其从源电极延伸到通道的第二部分的至少一部分上。 在器件工作期间,充电控制电极和通道之间的电位差可以控制通道的常开部分的开/关状态。

    Semiconductor Device with Breakdown Preventing Layer
    24.
    发明申请
    Semiconductor Device with Breakdown Preventing Layer 审中-公开
    具有故障防护层的半导体器件

    公开(公告)号:US20160071938A1

    公开(公告)日:2016-03-10

    申请号:US14942004

    申请日:2015-11-16

    Abstract: A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film. The conducting elements can be configured to split a high electric field spike otherwise present in the high-voltage surface region during operation of the device into multiple much smaller spikes.

    Abstract translation: 提供具有防分解层的半导体器件。 防破坏层可以位于器件的高压表面区域中。 防破坏层可以包括其中嵌入有导电元件的绝缘膜。 导电元件可以沿着绝缘膜的横向长度布置。 导电元件可以被配置为在设备操作期间将高电场尖峰分裂成另外存在于高电压表面区域中的多个更小的尖峰。

    Low-resistance electrode design
    25.
    发明授权
    Low-resistance electrode design 有权
    低电阻电极设计

    公开(公告)号:US09178025B2

    公开(公告)日:2015-11-03

    申请号:US14499652

    申请日:2014-09-29

    Abstract: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

    Abstract translation: 提供了一种用于设计半导体器件的方案,其中确定一对电极的两个或多个属性以例如使电极之间的电阻最小化。 每个电极可以包括多个指状件延伸的电流馈送触点,其以交替模式与另一个电极的指状物交叉指向。 属性可以包括每个手指的目标深度,每对相邻手指的目标有效宽度和/或当前馈送触点的一个或多个目标属性。 随后,可以制造包括该器件的器件和/或电路。

    Low-Resistance Electrode Design
    26.
    发明申请
    Low-Resistance Electrode Design 有权
    低电阻电极设计

    公开(公告)号:US20150014857A1

    公开(公告)日:2015-01-15

    申请号:US14499652

    申请日:2014-09-29

    Abstract: A solution for designing a semiconductor device, in which two or more attributes of a pair of electrodes are determined to, for example, minimize resistance between the electrodes, is provided. Each electrode can include a current feeding contact from which multiple fingers extend, which are interdigitated with the fingers of the other electrode in an alternating pattern. The attributes can include a target depth of each finger, a target effective width of each pair of adjacent fingers, and/or one or more target attributes of the current feeding contacts. Subsequently, the device and/or a circuit including the device can be fabricated.

    Abstract translation: 提供了一种用于设计半导体器件的方案,其中确定一对电极的两个或多个属性以例如使电极之间的电阻最小化。 每个电极可以包括多个指状件延伸的电流馈送触点,其以交替模式与另一个电极的指状物交叉指向。 属性可以包括每个手指的目标深度,每对相邻手指的目标有效宽度和/或当前馈送触点的一个或多个目标属性。 随后,可以制造包括该器件的器件和/或电路。

    SEMICONDUCTOR DEVICE WITH LOW-CONDUCTING BURIED AND/OR SURFACE LAYERS
    27.
    发明申请
    SEMICONDUCTOR DEVICE WITH LOW-CONDUCTING BURIED AND/OR SURFACE LAYERS 有权
    具有低导电性和/或表面层的半导体器件

    公开(公告)号:US20130126905A1

    公开(公告)日:2013-05-23

    申请号:US13682139

    申请日:2012-11-20

    Abstract: A device including one or more low-conducting layers is provided. A low-conducting layer can be located below the channel and one or more attributes of the low-conducting layer can be configured based on a minimum target operating frequency of the device and a charge-discharge time of a trapped charge targeted for removal by the low-conducting layer or a maximum interfering frequency targeted for suppression using the low-conducting layer. For example, a product of the lateral resistance and a capacitance between the low-conducting layer and the channel can be configured to be larger than an inverse of the minimum target operating frequency and the product can be smaller than at least one of: the charge-discharge time or an inverse of the maximum interfering frequency.

    Abstract translation: 提供了包括一个或多个低导电层的器件。 低导电层可以位于通道下方,并且可以基于器件的最小目标工作频率和针对要被除去的俘获电荷的充电 - 放电时间来配置低导电层的一个或多个属性 低导电层或使用低导电层抑制的最大干扰频率。 例如,横向电阻和低导电层和沟道之间的电容的乘积可以被配置为大于最小目标工作频率的倒数,并且乘积可以小于以下中的至少一个:电荷 - 充电时间或最大干扰频率的倒数。

Patent Agency Ranking