公开(公告)号：US10243100B2

公开(公告)日：2019-03-26

申请号：US15687606

申请日：2017-08-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Jinwei Yang ,  Remigijus Gaska ,  Mikhail Gaevski

IPC: H01L33/06 ,  H01L33/00 ,  H01L33/18 ,  H01L33/38 ,  H01S5/022 ,  H01L33/30 ,  H01S5/343 ,  H01S5/32 ,  H01S5/34

Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

公开(公告)号：US10158044B2

公开(公告)日：2018-12-18

申请号：US15391922

申请日：2016-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC: H01L31/072 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/06 ,  H01L21/02 ,  H01L29/15 ,  H01L33/02 ,  H01L33/04 ,  H01L33/20

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

公开(公告)号：US10153396B2

公开(公告)日：2018-12-11

申请号：US15857853

申请日：2017-12-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L27/15 ,  H01L31/0336 ,  H01L33/06 ,  H01L21/02 ,  H01L29/778 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L29/20 ,  H01L29/51 ,  H01L33/22

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US10032956B2

公开(公告)日：2018-07-24

申请号：US15495192

申请日：2017-04-24

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L33/32 ,  H01L33/00 ,  H01L33/10 ,  H01L33/06 ,  H01L33/24

CPC classification number: H01L33/22 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  Y02P90/265

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

公开(公告)号：US09923118B2

公开(公告)日：2018-03-20

申请号：US15225403

申请日：2016-08-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Alexander Dobrinsky ,  Rakesh Jain ,  Michael Shur

IPC: H01L33/10 ,  H01L33/32 ,  H01L33/00 ,  H01L33/12 ,  H01L33/46 ,  H01S5/022

CPC classification number: H01L33/10 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/12 ,  H01L33/32 ,  H01L33/46 ,  H01S5/0224

Abstract: A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. In one embodiment, the semiconductor layer is used to form an optoelectronic device.

公开(公告)号：US20170373222A1

公开(公告)日：2017-12-28

申请号：US15687606

申请日：2017-08-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Michael Shur ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Jinwei Yang ,  Remigijus Gaska ,  Mikhail Gaevski

IPC: H01L33/06 ,  H01S5/022 ,  H01L33/38 ,  H01L33/18 ,  H01L33/00 ,  H01S5/343 ,  H01L33/30 ,  H01S5/32 ,  H01S5/34

CPC classification number: H01L33/06 ,  H01L33/007 ,  H01L33/18 ,  H01L33/30 ,  H01L33/382 ,  H01L2224/14 ,  H01S5/0224 ,  H01S5/3209 ,  H01S5/3413 ,  H01S5/34333

Abstract: A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

公开(公告)号：US20170263805A1

公开(公告)日：2017-09-14

申请号：US15588896

申请日：2017-05-08

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L31/0224 ,  H01L31/0352 ,  H01L31/105 ,  H01L33/04 ,  H01L33/14 ,  H01L33/32

CPC classification number: H01L33/002 ,  H01L31/022408 ,  H01L31/035236 ,  H01L31/105 ,  H01L33/0062 ,  H01L33/025 ,  H01L33/04 ,  H01L33/145 ,  H01L33/32 ,  H01L2933/0008

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

公开(公告)号：US09653631B2

公开(公告)日：2017-05-16

申请号：US14475638

申请日：2014-09-03

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L31/0352 ,  H01L33/04 ,  H01L33/32

CPC classification number: H01L31/035272 ,  H01L33/04 ,  H01L33/32

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

公开(公告)号：US09647168B2

公开(公告)日：2017-05-09

申请号：US14944538

申请日：2015-11-18

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Maxim S. Shatalov ,  Jinwei Yang ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/14 ,  H01L33/04 ,  H01L33/32

CPC classification number: H01L33/002 ,  H01L31/022408 ,  H01L31/035236 ,  H01L31/105 ,  H01L33/0062 ,  H01L33/025 ,  H01L33/04 ,  H01L33/145 ,  H01L33/32 ,  H01L2933/0008

Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The p-type contact layer and electron blocking layer can be doped with a p-type dopant. The dopant concentration for the electron blocking layer can be at most ten percent the dopant concentration of the p-type contact layer. A method of designing such a heterostructure is also described.

公开(公告)号：US09634189B2

公开(公告)日：2017-04-25

申请号：US15138415

申请日：2016-04-26

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Rakesh Jain ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L21/02 ,  G06F17/50 ,  H01L33/00 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32

CPC classification number: H01L33/22 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/32 ,  H01L2224/16225

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.