公开(公告)号：US10297460B2

公开(公告)日：2019-05-21

申请号：US15496887

申请日：2017-04-25

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/15 ,  H01L31/0256 ,  H01L21/308 ,  H01L29/66 ,  H01L21/02 ,  H01L33/12 ,  H01L29/20 ,  H01L33/00

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US20180108806A1

公开(公告)日：2018-04-19

申请号：US15857853

申请日：2017-12-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/06 ,  H01L21/02 ,  H01L29/778 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L33/06 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0688 ,  H01L29/2003 ,  H01L29/518 ,  H01L29/7786 ,  H01L33/007 ,  H01L33/12 ,  H01L33/20 ,  H01L33/22 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0083 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US09799793B2

公开(公告)日：2017-10-24

申请号：US15391948

申请日：2016-12-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Daniel Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/06 ,  H01L33/00 ,  H01L33/32 ,  H01L33/12 ,  H01L29/778 ,  H01L29/66 ,  H01L33/20 ,  H01L33/24

CPC classification number: H01L33/0025 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

公开(公告)号：US20170229611A1

公开(公告)日：2017-08-10

申请号：US15496887

申请日：2017-04-25

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/12 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/158 ,  H01L29/2003 ,  H01L29/66075 ,  H01L33/007 ,  H01L33/12

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US20160322535A1

公开(公告)日：2016-11-03

申请号：US15212659

申请日：2016-07-18

Applicant: Sensor Electronic Technology, Inc.

Inventor： Rakesh Jain ,  Wenhong Sun ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/22 ,  H01L33/12 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L33/06 ,  H01L33/10 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32 ,  H01L29/34

CPC classification number: H01L33/22 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02658 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/34 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L33/007 ,  H01L33/06 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2933/0091

Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.

公开(公告)号：US20130193480A1

公开(公告)日：2013-08-01

申请号：US13756806

申请日：2013-02-01

Applicant: Sensor Electronic Technology, Inc.

Inventor： Wenhong Sun ,  Rakesh Jain ,  Jinwei Yang ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Remigijus Gaska ,  Michael Shur

IPC: H01L21/02 ,  H01L29/06

CPC classification number: H01L21/02587 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/0684 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/16

Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer. One or more of a set of growth conditions, a thickness of one or both of the layers, and/or a lattice mismatch between the layers can be configured to create a target level of compressive and/or shear stress within a minimum percentage of the interface between the layers.

Abstract translation: 提供了一种用于制造半导体结构的解决方案。 半导体结构包括使用一组外延生长周期在衬底上生长的多个半导体层。 在每个外延生长周期期间，生长具有拉伸应力或压缩应力之一的第一半导体层，然后直接在第一半导体层上生长具有另一个的拉伸应力或压缩应力的第二半导体层。 一组生长条件中的一个或多个层中的一个或两个的厚度和/或层之间的晶格失配可以被配置为在最小百分比的范围内产生压缩和/或剪切应力的目标水平 层之间的界面。

公开(公告)号：US10164147B2

公开(公告)日：2018-12-25

申请号：US15662675

申请日：2017-07-28

Applicant: Sensor Electronic Technology, Inc.

Inventor： Wenhong Sun ,  Alexander Dobrinsky ,  Maxim S. Shatalov ,  Jinwei Yang ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/06 ,  H01L33/00 ,  H01L33/04 ,  H01L21/02

Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.

公开(公告)号：US20170338371A1

公开(公告)日：2017-11-23

申请号：US15660191

申请日：2017-07-26

Applicant: Sensor Electronic Technology, Inc.

Inventor： Daniel Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L33/00 ,  H01L33/24 ,  H01L33/12 ,  H01L29/66 ,  H01L29/778 ,  H01L33/32 ,  H01L33/20

CPC classification number: H01L33/0025 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/12 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

公开(公告)号：US09735315B2

公开(公告)日：2017-08-15

申请号：US15265975

申请日：2016-09-15

Applicant: Sensor Electronic Technology, Inc.

Inventor： Daniel Billingsley ,  Robert M. Kennedy ,  Wenhong Sun ,  Rakesh Jain ,  Maxim S. Shatalov ,  Alexander Dobrinsky ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/06 ,  H01L33/12 ,  H01L33/32 ,  H01L33/00 ,  H01L21/02 ,  H01L29/15 ,  H01L29/20 ,  H01L33/20 ,  H01L33/24 ,  H01L33/06

CPC classification number: H01L33/12 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/155 ,  H01L29/2003 ,  H01L33/0025 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/06 ,  H01L33/20 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225

Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.

公开(公告)号：US20160211331A1

公开(公告)日：2016-07-21

申请号：US15083423

申请日：2016-03-29

Applicant: Sensor Electronic Technology, Inc.

Inventor： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/06 ,  H01L29/205

CPC classification number: H01L29/158 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/007 ,  H01L33/12

Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

Abstract translation: 提供了诸如III族氮化物基半导体结构的半导体结构。 半导体结构包括含有半导体层的空腔。 含腔的半导体层可以具有大于两个单层和多个空腔的厚度。 空腔可以具有至少一纳米的特征尺寸和至少五纳米的特征分离。