CONCURRENT LISTENING
    21.
    发明公开

    公开(公告)号:US20230371067A1

    公开(公告)日:2023-11-16

    申请号:US17743042

    申请日:2022-05-12

    CPC classification number: H04W74/0808 H04W74/04 H04L5/0053 H04W4/80 H04W4/23

    Abstract: A wireless communication device has a receiver to listen to a sequence of channels. A controller responds to a preamble being detected on a first channel while the receiver is tuned to the first channel by causing the receiver to stay on the first channel and decode packet(s) associated with the preamble. The controller responds to detection of a first symbol of a first transmission protocol and the preamble not being detected to cause the receiver to stay on the first channel for a predetermined time waiting for a retry. The controller responds to detection of a second symbol of a second transmission protocol and the preamble not being detected to cause the receiver to switch to an advertising channel of the second transmission protocol. If no preambles, noise, or symbols are detected, the receiver switches to listening to a next channel in the sequence after a fixed time.

    FAST FREQUENCY SYNTHESIZER SWITCHING
    22.
    发明公开

    公开(公告)号:US20230318609A1

    公开(公告)日:2023-10-05

    申请号:US17709642

    申请日:2022-03-31

    CPC classification number: H03L7/1075 H04B1/40 H03L7/099

    Abstract: A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.

    DUAL-BAND OPERATION OF A RADIO DEVICE

    公开(公告)号:US20230099832A1

    公开(公告)日:2023-03-30

    申请号:US17490255

    申请日:2021-09-30

    Abstract: In one embodiment, an integrated circuit includes: a first radio frequency (RF) circuit configured to receive and process a first RF signal having a sub-gigahertz (GHz) frequency to output a first lower frequency signal and to transmit RF signals having the sub-GHz frequency; a second RF circuit configured to receive and process a second RF signal having a frequency of at least substantially 2.4 GHz to output a second lower frequency signal and to transmit RF signals at the at least substantially 2.4 GHz; shared analog circuitry coupled to the first RF circuit and the second RF circuit, the shared analog circuitry to receive at least one of the first RF signal or the second RF signal and output a digital output signal; and a digital circuit coupled to the shared analog circuit, the digital circuit to recover message information from the digital output signal.

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