公开(公告)号：US20200175379A1

公开(公告)日：2020-06-04

申请号：US16699727

申请日：2019-12-01

Applicant: Tsinghua University

Inventor： Huaqiang Wu ,  Bin Gao ,  Yudeng Lin ,  He Qian

IPC: G06N3/08 ,  G06N3/06 ,  G06N3/04

Abstract: A generative adversarial network device and a training method thereof. The generative adversarial network device includes a generator and a discriminator. The generator is configured to generate a first sample according to an input data; the discriminator is coupled to the generator, and is configured to receive the first sample and be trained based on the first sample; the generator includes a first memristor array serving as a first weight array. The generative adversarial network device can omit a process of adding noise to fake samples generated by the generator, thereby saving training time, reducing resource consumption and improving training speed of the generative adversarial network.

公开(公告)号：US20180330788A1

公开(公告)日：2018-11-15

申请号：US15776520

申请日：2016-12-22

Applicant: Tsinghua University

Inventor： Chen Wang ,  Huaqiang Wu ,  He Qian ,  Bin Gao

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0064 ,  G11C2013/0092 ,  G11C2213/79 ,  G11C2213/82

Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.

公开(公告)号：US09712124B2

公开(公告)日：2017-07-18

申请号：US14798940

申请日：2015-07-14

Applicant: Tsinghua University

Inventor： Huaqiang Wu ,  Hongming Lyu ,  He Qian ,  Zhiping Yu ,  Yilin Huang ,  Jinyu Zhang

IPC: H03F3/60 ,  H03F1/56 ,  H03F3/193 ,  H03F1/18

CPC classification number: H03F1/565 ,  H03F1/18 ,  H03F3/193 ,  H03F3/607 ,  H03F2200/301 ,  H03F2200/451

Abstract: The present disclosure provides a distributed amplifier, including: a drain transmission line; a gate transmission line; GFETs, in which sources of the graphene field-effect transistors are respectively grounded; gates of the graphene field-effect transistors respectively connected with a plurality of first shunt capacitors which are grounded; the gate transmission line is connected with a plurality of first nodes respectively between the gates of the graphene field-effect transistors and the plurality of first shunt capacitors, having a plurality of first inductors respectively between each two first nodes; drains of the graphene field-effect transistors respectively connected with a plurality of second shunt capacitors which are grounded; the drain transmission line is connected with a plurality of second nodes respectively between the drains of the graphene field-effect transistors and the plurality of second shunt capacitors, having a plurality of second inductors respectively between each two second nodes.

公开(公告)号：US20210049448A1

公开(公告)日：2021-02-18

申请号：US16964435

申请日：2018-02-24

Applicant: Tsinghua University

Inventor： Xinyi LI ,  Huaqiang Wu ,  He Qian ,  Bin Gao ,  Sen Song ,  Qingtian Zhang

IPC: G06N3/06 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

公开(公告)号：US20210028358A1

公开(公告)日：2021-01-28

申请号：US17037039

申请日：2020-09-29

Applicant: Tsinghua University

Inventor： Huaqiang Wu ,  Wei Wu ,  Bin Gao ,  He Qian

IPC: H01L45/00

Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

公开(公告)号：US20200237311A1

公开(公告)日：2020-07-30

申请号：US16751110

申请日：2020-01-23

Applicant: Tsinghua University

Inventor： Xinyi Li ,  Huaqiang Wu ,  He Qian ,  Bin Gao

IPC: A61B5/00 ,  A61B5/04 ,  A61B5/0488 ,  A61B5/048 ,  G11C13/00

Abstract: A signal processing device and a signal processing method. The signal processing device includes a receiver, a memristor array and a classifier. The receiver is configured to receive a first signal. The memristor array includes a plurality of memristor units, each of the plurality of memristor units includes a memristor, and the memristor array is configured to apply the first signal that has been received to at least one memristor unit of the plurality of memristor units and output a second signal based on a memristor resistance value distribution of the memristor array. The classifier is configured to classify the second signal outputted from the memristor array to obtain a type of the first signal.

公开(公告)号：US10475512B2

公开(公告)日：2019-11-12

申请号：US15776520

申请日：2016-12-22

Applicant: Tsinghua University

Inventor： Chen Wang ,  Huaqiang Wu ,  He Qian ,  Bin Gao

IPC: G11C11/00 ,  G11C13/00

Abstract: An operation method of a resistance random access memory and a resistance random access memory apparatus are provided. The method includes: applying an initial reset voltage to a storage unit; carrying out a read check operation to acquire a resistance value of the storage unit; judging whether the resistance value of the storage unit reaches a preset target resistance value in a high resistance state; if the resistance value of the storage unit is less than the preset target resistance value in the high resistance state, applying a set voltage to the storage unit to set the storage unit to a preset target resistance value in a low resistance state, then applying a reset voltage of which an amount is increased to the storage unit, and repeating the read check operation and the subsequent steps until the storage unit reaches the preset target resistance value in the high resistance state.

公开(公告)号：US10468099B2

公开(公告)日：2019-11-05

申请号：US16132931

申请日：2018-09-17

Applicant: Tsinghua University

Inventor： Huaqiang Wu ,  Yachuan Pang ,  Bin Gao ,  He Qian

IPC: G11C11/00 ,  G11C13/00 ,  H04L9/32 ,  H01L27/24 ,  G09C1/00

Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.