Circuit structure and driving method thereof, neural network

    公开(公告)号:US11468300B2

    公开(公告)日:2022-10-11

    申请号:US16071985

    申请日:2017-11-14

    Abstract: A circuit structure and a driving method thereof, a neural network are disclosed. The circuit structure includes at least one circuit unit, each circuit unit includes a first group of resistive switching devices and a second group of resistive switching devices, the first group of resistive switching devices includes a resistance gradual-change device, the second group of resistive switching devices includes a resistance abrupt-change device, the first group of resistive switching devices and the second group of resistive switching devices are connected in series, in a case that no voltage is applied, a resistance value of the first group of resistive switching devices is larger than a resistance value of the second group of resistive switching devices.

    Resistive random access memory and manufacturing method thereof

    公开(公告)号:US11355704B2

    公开(公告)日:2022-06-07

    申请号:US17037039

    申请日:2020-09-29

    Abstract: A resistive random access memory and a manufacture method thereof are provided. The resistive random access memory includes: a first electrode, a second electrode, a resistive layer between the first electrode and the second electrode, and at least one thermal enhanced layer; the thermal enhanced layer is adjacent to the resistive layer, and a thermal conductivity of the thermal enhanced layer is less than a thermal conductivity of the first electrode and a thermal conductivity of the second electrode.

    Circuit Structure and Driving Method Thereof, Chip and Authentication Method Thereof, and Electronic Device

    公开(公告)号:US20190088325A1

    公开(公告)日:2019-03-21

    申请号:US16132931

    申请日:2018-09-17

    Abstract: A circuit structure for implementing a physical unclonable function and a driving method thereof, an integrated circuit chip and an authentication method thereof, an electronic device are disclosed. The circuit structure includes: a multilayer circuit, a first address circuit and an output circuit, the multilayer circuit includes a first RRAM device array which is addressable and a second RRAM device array which is addressable; the first address circuit is configured to map a resistance value of a second RRAM device in the second RRAM device array to a first address; the first address is used for positioning a selected first RRAM device; and the output circuit is configured to acquire and process a resistance value of the selected first RRAM device and output a processing result.

    Data processing method based on memristor array and electronic apparatus

    公开(公告)号:US12283320B2

    公开(公告)日:2025-04-22

    申请号:US17788408

    申请日:2021-12-14

    Abstract: A data processing method based on a memristor array and an electronic apparatus are disclosed. The data processing method based on a memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing data corresponding to a convolution parameter matrix of a convolution processing into the memristor array; inputting the plurality of first analog signals respectively into a plurality of column signal input terminals of the memristor array that has been set, controlling operation of the memristor array to perform the convolution processing on the plurality of first analog signals, and obtaining a plurality of second analog signals after performing the convolution processing at a plurality of row signal output terminals of the memristor array, respectively.

    Neural network and its information processing method, information processing system

    公开(公告)号:US12217164B2

    公开(公告)日:2025-02-04

    申请号:US16964435

    申请日:2018-02-24

    Abstract: A neural network and its information processing method, information processing system. The neural network includes N layers of neuron layers connected to each other one by one, except for a first layer of neuron layer, each of the neurons of the other neuron layers includes m dendritic units and one hippocampal unit; the dendritic unit includes a resistance value graded device, the hippocampal unit includes a resistance value mutation device, and the m dendritic units can be provided with different threshold voltage or current, respectively; and the neurons on the nth layer neuron layer are connected to the m dendritic units of the neurons on the n+1th layer neuron layer; wherein N is an integer larger than 3, m is an integer larger than 1, n is an integer larger than 1 and less than N.

    Storage device and data writing method

    公开(公告)号:US12100448B2

    公开(公告)日:2024-09-24

    申请号:US17530128

    申请日:2021-11-18

    CPC classification number: G11C13/0069 G06N3/065 G11C2013/0078 G11C2213/15

    Abstract: A storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory (1T1R). The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

    Compilation method, apparatus, computing device and medium

    公开(公告)号:US11803360B2

    公开(公告)日:2023-10-31

    申请号:US17517096

    申请日:2021-11-02

    CPC classification number: G06F8/443 G06F17/16 G06N3/10

    Abstract: A compilation method, a compilation apparatus suitable for an In-Memory Computing apparatus, a computing device and a storage medium. The compilation method includes: acquiring calculation information of an algorithm to be compiled; converting the algorithm to be compiled into the first intermediate representation according to the calculation information; mapping the first intermediate representation to the second intermediate representation; and compiling the algorithm to be compiled into instruction information recognized by the In-Memory Computing apparatus according to the hardware information, to make the In-Memory Computing apparatus execute the instruction information. The compilation method may compile the calculation information into instructions that may be directly executed by the In-Memory Computing apparatus, so as to realize the effect of accelerating the operations of various algorithms by using the In-Memory Computing apparatus.

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