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    Semiconductor structure
    23.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US09859282B1

    公开(公告)日：2018-01-02

    申请号：US15280333

    申请日：2016-09-29

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Shu-Ru Wang

    IPC: H01L27/108 ,  H01L29/78

    CPC classification number: H01L27/10805 ,  H01L27/0207 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

    Abstract: A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.

    Method for forming patterns
    25.
    发明授权
    Method for forming patterns 有权
    形成图案的方法

    公开(公告)号：US09316901B2

    公开(公告)日：2016-04-19

    申请号：US14259173

    申请日：2014-04-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Yu Chen ,  Chia-Wei Huang ,  Chun-Hsien Huang ,  Shih-Chun Tsai ,  Kai-Lin Chuang

    IPC: G03F9/00 ,  G03F1/36 ,  G03F1/70 ,  G03F1/68

    CPC classification number: G03F1/36 ,  G03F1/00 ,  G03F1/68 ,  G03F1/70

    Abstract: A method for forming patterns includes the following steps. A first layout including a first target pattern and a first unprintable dummy pattern is provided. A second layout including a second target pattern and a second printable dummy pattern are provided, wherein at least part of the second printable dummy pattern overlaps the first unprintable dummy pattern exposure limit, such that the second printable dummy pattern cannot be formed in a wafer.

    Abstract translation: 形成图案的方法包括以下步骤。 提供了包括第一目标图案和第一不可打印虚设图案的第一布局。 提供包括第二目标图案和第二可打印虚拟图案的第二布局，其中第二可打印虚拟图案的至少一部分与第一不可打印虚设图案曝光极限重叠，使得第二可打印虚设图案不能形成在晶片中。

    STRESS MEMORIZATION PROCESS AND SEMICONDUCTOR STRUCTURE INCLUDING CONTACT ETCH STOP LAYER
    26.
    发明申请
    STRESS MEMORIZATION PROCESS AND SEMICONDUCTOR STRUCTURE INCLUDING CONTACT ETCH STOP LAYER 审中-公开
    应力记忆过程和半导体结构，包括接触蚀刻停止层

    公开(公告)号：US20150228788A1

    公开(公告)日：2015-08-13

    申请号：US14179563

    申请日：2014-02-13

    Applicant: United Microelectronics Corp.

    Inventor： Chun-Feng Chen ,  Wen-Yu Yang ,  Yu-Cheng Tung ,  Chun-Hsien Huang ,  Hui-Shen Shih ,  Shih-Chang Chang

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/7847 ,  H01L21/76832 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636

    Abstract: A stress memorization process including the following step is provided. A gate is formed on a substrate. A low-k dielectric layer with a dielectric constant lower than 3 is formed to entirely cover the gate and the substrate. A stress layer is formed to entirely cover the low-k dielectric layer. The stress layer and the low-k dielectric layer are removed. Moreover, a semiconductor structure including a contact etch stop layer is provided. A gate is disposed on a substrate. A porous layer entirely covers the gate and the substrate. A contact etch stop layer entirely covers the porous layer, wherein the thickness of the porous layer is thinner than the thickness of the contact etch stop layer.

    Abstract translation: 提供包括以下步骤的应力记忆过程。 栅极形成在基板上。 形成介电常数低于3的低k电介质层，以完全覆盖栅极和衬底。 形成应力层以完全覆盖低k电介质层。 去除应力层和低k电介质层。 此外，提供了包括接触蚀刻停止层的半导体结构。 栅极设置在基板上。 多孔层完全覆盖栅极和衬底。 接触蚀刻停止层完全覆盖多孔层，其中多孔层的厚度比接触蚀刻停止层的厚度薄。

    Method for Forming Photo-masks and OPC Method
    27.
    发明申请
    Method for Forming Photo-masks and OPC Method 审中-公开
    形成光罩和OPC方法的方法

    公开(公告)号：US20140282295A1

    公开(公告)日：2014-09-18

    申请号：US13802833

    申请日：2013-03-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Hsien Huang ,  Ming-Jui Chen ,  Ching-Chun Huang ,  Chia-Wei Huang ,  Yu-Feng Chao ,  Yu-Chuan Chang

    IPC: G06F17/50

    CPC classification number: H01L21/76816 ,  G03F1/36 ,  H01L21/76807

    Abstract: The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method.

    Abstract translation: 本发明提供一种至少形成光掩模的方法。 提供与第一结构相关的第一光掩模图案。 提供与第二结构相关的第二光掩模图案。 提供了与第三结构相关的第三光掩模图案。 第一结构，第二结构和第三结构依次设置在半导体结构中。 提供了包括比较步骤的光学邻近处理，其中比较步骤包括比较第一光掩模图案和第三光掩模图案。 最后，导入第一光掩模图案以形成第一掩模，第二光掩模图案被导入以形成第二掩模，并且导入第三光掩模图案以形成第三掩模。 本发明还提供一种OPC方法。

    Layout pattern of static random-access memory
    28.
    发明申请
    Layout pattern of static random-access memory 有权

    公开(公告)号：US20250142799A1

    公开(公告)日：2025-05-01

    申请号：US18398227

    申请日：2023-12-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Tsung-Hsun Wu ,  Liang-Wei Chiu ,  Chun-Hsien Huang

    IPC: H10B10/00

    Abstract: The invention provides a layout pattern of static random-access memory (SRAM), which comprises a substrate, wherein a plurality of diffusion regions and a plurality of gate structures are located on the substrate to form a plurality of transistors, wherein the plurality of gate structures comprise a first gate structure, which has a stepped shape when viewed from a top view, and the first gate structure spans a first diffusion region and a second diffusion region to form a first access transistor (PG1), wherein the first diffusion region is adjacent to and in direct contact with the second diffusion region.

    Layout of semiconductor memory device
    29.
    发明授权
    Layout of semiconductor memory device 有权

    公开(公告)号：US11915755B2

    公开(公告)日：2024-02-27

    申请号：US17580591

    申请日：2022-01-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Shu-Ru Wang ,  Chun-Hsien Huang ,  Hsin-Chih Yu ,  Meng-Ping Chuang ,  Li-Ping Huang ,  Yu-Fang Chen

    IPC: G11C15/04

    CPC classification number: G11C15/04

    Abstract: A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells, where at least two of the TCAM bit cells are mirror-symmetrical along an axis of symmetry, and each of the TCAM bit cells includes two storage units electrically connected to two word lines respectively, and a logic circuit electrically connected to the storage units. The logic circuit includes two first reading transistors, and two second reading transistors, where each of the second reading transistors includes a gate and source and drain regions, the source and drain regions of the second reading transistors are electrically connected to two matching lines and the first reading transistors, respectively, where the word lines are disposed parallel to and between the matching lines.

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