公开(公告)号：US09640484B2

公开(公告)日：2017-05-02

申请号：US14882424

申请日：2015-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Hsien Lin ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L23/535 ,  H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/16 ,  H01L29/24 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/28525 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same, the semiconductor device includes a fin shaped structure, a gate structure, an epitaxial layer, a germanium layer, an interlayer dielectric layer and a first plug. The fin shaped structure is disposed on a substrate. The gate structure is formed across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure adjacent to the gate structure. The germanium layer is disposed on the epitaxial layer. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is disposed in the interlayer dielectric layer to contact the germanium layer.

公开(公告)号：US09548239B2

公开(公告)日：2017-01-17

申请号：US14612235

申请日：2015-02-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Feng-Yi Chang ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Yi-Kuan Wu ,  Ying-Cheng Liu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/76 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/76816 ,  H01L21/76879

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract translation: 首先在衬底上形成栅极结构，并且在栅极结构周围形成层间电介质（ILD）层，在ILD层和栅极结构上形成介电层，在介电层和ILD层中形成开口 并且在介质层和开口中形成有机电介质层（ODL）。 在去除部分ODL后，部分电介质层延伸开口，然后剩余的ODL，在开口处形成接触塞。

公开(公告)号：US09490334B2

公开(公告)日：2016-11-08

申请号：US14510126

申请日：2014-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/823842 ,  H01L27/0883 ,  H01L27/092 ,  H01L29/165 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/513 ,  H01L29/66628

Abstract: A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first work function metal layer, and the first work function metal layer includes a taper top. The second metal gate includes a second work function metal layer. The first work function metal layer and the second work function metal layer are complementary to each other.

Abstract translation: 具有金属栅极的半导体器件包括衬底，位于衬底上的第一金属栅极和位于衬底上的第二金属栅极。 第一金属栅极包括第一功函数金属层，第一功函数金属层包括锥形顶部。 第二金属栅极包括第二功函数金属层。 第一功函数金属层和第二功函数金属层彼此互补。

公开(公告)号：US09455135B2

公开(公告)日：2016-09-27

申请号：US14562768

申请日：2014-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  En-Chiuan Liou ,  Chieh-Te Chen

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/311 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0206 ,  H01L21/02186 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a hard mask on the gate structure and the ILD layer; forming a first patterned mask layer on the hard mask; using the first patterned mask layer to remove part of the hard mask for forming a patterned hard mask; and utilizing a gas to strip the first patterned mask layer while forming a protective layer on the patterned hard mask, wherein the gas is selected from the group consisting of N2 and O2.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层; 在栅极结构和ILD层上形成硬掩模; 在硬掩模上形成第一图案化掩模层; 使用第一图案化掩模层去除用于形成图案化硬掩模的硬掩模的一部分; 并且利用气体剥离第一图案化掩模层，同时在图案化的硬掩模上形成保护层，其中气体选自N2和O2。

公开(公告)号：US20160268203A1

公开(公告)日：2016-09-15

申请号：US14681119

申请日：2015-04-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Wei-Hao Huang

IPC: H01L23/535 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3115 ,  H01L21/311

CPC classification number: H01L29/78 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76897 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least a gate structure thereon and an interlayer dielectric (ILD) layer surrounding the gate structure, wherein the gate structure comprises a hard mask thereon; forming a dielectric layer on the gate structure and the ILD layer; removing part of the dielectric layer to expose the hard mask and the ILD layer; and performing a surface treatment to form a doped region in the hard mask and the ILD layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上至少具有栅极结构的衬底和围绕栅极结构的层间电介质（ILD）层，其中栅极结构包括其上的硬掩模; 在栅极结构和ILD层上形成介电层; 去除介电层的一部分以暴露硬掩模和ILD层; 并进行表面处理以在硬掩模和ILD层中形成掺杂区域。

公开(公告)号：US20160104645A1

公开(公告)日：2016-04-14

申请号：US14536696

申请日：2014-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Yi-Wei Chen ,  Chien-Ting Lin ,  Shih-Fang Tzou ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/823437 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/495 ,  H01L29/4966

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a plurality of gate structures on the substrate; forming a first stop layer on the gate structures; forming a second stop layer on the first stop layer; forming a first dielectric layer on the second stop layer; forming a plurality of first openings in the first dielectric layer to expose the second stop layer; forming a plurality of second openings in the first dielectric layer and the second stop layer to expose the first stop layer; and removing part of the second stop layer and part of the first stop layer to expose the gate structures.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成多个栅极结构; 在栅极结构上形成第一阻挡层; 在所述第一停止层上形成第二停止层; 在所述第二停止层上形成第一电介质层; 在所述第一电介质层中形成多个第一开口以露出所述第二阻挡层; 在所述第一介电层和所述第二停止层中形成多个第二开口以暴露所述第一停止层; 以及去除所述第二停止层的一部分和所述第一停止层的一部分以暴露所述栅极结构。

公开(公告)号：US20150325453A1

公开(公告)日：2015-11-12

申请号：US14273283

申请日：2014-05-08

Applicant: United Microelectronics Corp.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Cheng-Hsing Chuang

IPC: H01L21/311

CPC classification number: H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

Abstract: A method of forming a semiconductor device is provided. A material layer, a first flowing material layer and a first mask layer are sequentially formed on a substrate. A first etching process is performed by using the first mask layer as a mask, so as to form a first opening in the material layer. The first mask layer and the first flowing material layer are removed. A filler layer is formed in the first opening. A second flowing material layer is formed on the material layer and the filler layer. A second mask layer is formed on the second flowing material layer. A second etching process is performed by using the second mask layer as a mask, so as to form a second opening in the material layer.

Abstract translation: 提供一种形成半导体器件的方法。 在基板上依次形成材料层，第一流动材料层和第一掩模层。 通过使用第一掩模层作为掩模来进行第一蚀刻工艺，以在材料层中形成第一开口。 去除第一掩模层和第一流动材料层。 在第一开口中形成填充层。 在材料层和填料层上形成第二流动材料层。 在第二流动材料层上形成第二掩模层。 通过使用第二掩模层作为掩模来进行第二蚀刻处理，以在材料层中形成第二开口。

公开(公告)号：US12206007B2

公开(公告)日：2025-01-21

申请号：US17868753

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.

公开(公告)号：US11881409B2

公开(公告)日：2024-01-23

申请号：US17359669

申请日：2021-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hao Huang ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Lung-En Kuo ,  Chia-Wei Hsu

IPC: H01L21/308 ,  H01L21/306 ,  H01L21/027 ,  G03F1/38

CPC classification number: H01L21/3085 ,  H01L21/0274 ,  H01L21/30604 ,  G03F1/38

Abstract: A method of cutting fins includes the following steps. A photomask including a snake-shape pattern is provided. A photoresist layer is formed over fins on a substrate. A photoresist pattern in the photoresist layer corresponding to the snake-shape pattern is formed by exposing and developing. The fins are cut by transferring the photoresist pattern and etching cut parts of the fins.

公开(公告)号：US20230411489A1

公开(公告)日：2023-12-21

申请号：US17868753

申请日：2022-07-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Wen Zhang ,  Kun-Chen Ho ,  Chun-Lung Chen ,  Chung-Yi Chiu ,  Ming-Chou Lu

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4991 ,  H01L29/7833 ,  H01L29/41775 ,  H01L29/66492 ,  H01L29/401

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an interlayer dielectric (ILD) layer on the gate structure, forming a contact hole in the ILD layer adjacent to the gate structure, performing a plasma doping process to form a doped layer in the ILD layer and a source/drain region adjacent to the gate structure, forming a conductive layer in the contact hole, planarizing the conductive layer to form a contact plug, removing the doped layer to form an air gap adjacent to the contact plug, and then forming a stop layer on the ILD layer and the contact plug.