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公开(公告)号：US20150093870A1
公开(公告)日：2015-04-02
申请号：US14042224
申请日：2013-09-30
Applicant: United Microelectronics Corp.
Inventor： Yen-Liang Wu , Chung-Fu Chang , Yu-Hsiang Hung , Ssu-I Fu , Chien-Ting Lin , Shih-Fang Tzou
IPC: H01L21/28 , H01L21/311 , H01L29/66
CPC classification number: H01L21/31111 , H01L21/3086 , H01L21/31116 , H01L29/165 , H01L29/517 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
Abstract: A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.
Abstract translation: 提供一种制造半导体器件结构的方法。 该方法包括以下步骤。 在基板上形成栅极电介质层。 栅极电极位于栅极电介质层上。 处理由栅电极露出的栅介电层。 执行第一蚀刻工艺以去除由栅电极暴露的栅介质层的至少一部分。 在栅电极的侧壁上形成间隔物。 执行第二蚀刻工艺以在栅电极旁边的基板中形成凹部。 此外，在第一蚀刻工艺和第二蚀刻工艺期间，经处理的栅极电介质层的蚀刻速率大于未处理的栅极介电层的蚀刻速率。
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公开(公告)号：US20240349493A1
公开(公告)日：2024-10-17
申请号：US18754195
申请日：2024-06-26
Inventor： Yi-Wei Chen , Hsu-Yang Wang , Chun-Chieh Chiu , Shih-Fang Tzou
IPC: H10B12/00 , H01L21/768
CPC classification number: H10B12/485 , H01L21/76804 , H01L21/76805 , H01L21/76814 , H01L21/76819 , H01L21/76895 , H10B12/053 , H10B12/482
Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
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公开(公告)号：US20230369215A1
公开(公告)日：2023-11-16
申请号：US18226750
申请日：2023-07-26
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Chien-Cheng Tsai , Feng-Ming Huang
IPC: H01L23/528 , H01L21/311 , H01L21/768 , H01L23/522 , H01L21/762 , H01L29/06 , H10B12/00
CPC classification number: H01L23/5283 , H01L21/31111 , H01L21/76831 , H01L23/5226 , H01L21/76802 , H01L21/76877 , H01L21/76224 , H01L29/0649 , H10B12/482 , H10B12/485
Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
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公开(公告)号：US11769727B2
公开(公告)日：2023-09-26
申请号：US17467287
申请日：2021-09-06
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Chien-Cheng Tsai , Feng-Ming Huang
IPC: H01L23/52 , H01L23/528 , H01L21/311 , H01L21/768 , H01L23/522 , H01L21/762 , H01L29/06 , H10B12/00
CPC classification number: H01L23/5283 , H01L21/31111 , H01L21/76224 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L23/5226 , H01L29/0649 , H10B12/482 , H10B12/485
Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
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公开(公告)号：US20230097175A1
公开(公告)日：2023-03-30
申请号：US18076419
申请日：2022-12-07
Inventor： Li-Wei Feng , Shih-Fang Tzou , Chien-Ting Ho , Ying-Chiao Wang , Yu-Ching Chen , Hui-Ling Chuang , Kuei-Hsuan Yu
IPC: H01L27/108 , H01L21/768
Abstract: A semiconductor structure with a capacitor landing pad includes a substrate. A capacitor contact plug is disposed on the substrate. A capacitor landing pad contacts and electrically connects the capacitor contact plug. A bit line is disposed on the substrate. A dielectric layer surrounds the capacitor landing pad. The dielectric layer includes a bottom surface lower than a top surface of the bit line.
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Patent Agency Ranking
公开(公告)号：US20210398902A1
公开(公告)日：2021-12-23
申请号：US17467287
申请日：2021-09-06
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Chien-Cheng Tsai , Feng-Ming Huang
IPC: H01L23/528 , H01L21/311 , H01L27/108 , H01L21/768 , H01L23/522 , H01L21/762 , H01L29/06
Abstract: A semiconductor memory device and a manufacturing method thereof are provided in the present invention. An under-cut structure is formed at an edge of a bit line contact opening in the process of forming the bit line contact opening for avoiding short problems caused by alignment shifting, and the process window of the process of forming the bit line contact opening may be improved accordingly.
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公开(公告)号：US20200212048A1
公开(公告)日：2020-07-02
申请号：US16258657
申请日：2019-01-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Gang-Yi Lin , Shih-Fang Tzou , Fu-Che Lee , Feng-Yi Chang , Ying-Chih Lin , Kai-Lou Huang , Yi-Ching Chang
IPC: H01L27/108
Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
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公开(公告)号：US10685868B2
公开(公告)日：2020-06-16
申请号：US16553202
申请日：2019-08-28
Inventor： Feng-Yi Chang , Shih-Fang Tzou , Fu-Che Lee , Hsin-Yu Chiang , Yu-Ching Chen
IPC: H01L21/4763 , H01L21/768 , H01L21/311
Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
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公开(公告)号：US10658365B2
公开(公告)日：2020-05-19
申请号：US16052636
申请日：2018-08-02
Inventor： Li-Wei Feng , Shih-Fang Tzou , Chien-Cheng Tsai , Chih-Chi Cheng , Chia-Wei Wu , Ger-Pin Lin
IPC: H01L27/108
Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.
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公开(公告)号：US10347642B2
公开(公告)日：2019-07-09
申请号：US15856024
申请日：2017-12-27
Inventor： Feng-Yi Chang , Chien-Ting Ho , Shih-Fang Tzou , Fu-Che Lee
Abstract: A manufacturing method of a semiconductor memory device is provided in the present invention. A cleaning treatment to a storage node contact on a semiconductor substrate is performed, and a metal silicide layer is formed after the cleaning treatment. A gate contact opening penetrating a capping layer of a transistor on the semiconductor substrate is formed after the step of forming the metal silicide layer for exposing a gate structure of the transistor. By the manufacturing method of the semiconductor memory device in the present invention, the gate structure of the transistor may be kept from being influenced and/or damaged by the cleaning treatment of the storage node contact, and the electrical performance of the transistor may be ensured accordingly.
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