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    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160020323A1

    公开(公告)日：2016-01-21

    申请号：US14463676

    申请日：2014-08-20

    Applicant: United Microelectronics Corp.

    Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Wen-Jiun Shen ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Yi-Wei Chen

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

    Abstract: A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.

    Abstract translation: 半导体器件包括鳍结构，绝缘结构，突出结构，外延结构和栅极结构。 翅片结构和绝缘结构设置在基板上。 突出结构与基板直接接触，并从绝缘结构部分突出，突出结构为翅片结构。 外延结构设置在翅片结构的顶表面上并完全覆盖翅片结构的顶表面。 此外，外延结构具有弯曲的顶表面。 栅极结构覆盖鳍结构和外延结构。

    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
    半导体器件及其形成方法

    公开(公告)号：US20160020110A1

    公开(公告)日：2016-01-21

    申请号：US14462114

    申请日：2014-08-18

    Applicant: United Microelectronics Corp.

    Inventor： Man-Ling Lu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Yen-Liang Wu ,  Wen-Jiun Shen ,  Chia-Jong Liu ,  Ssu-I Fu ,  Yi-Wei Chen

    IPC: H01L21/308 ,  H01L29/78

    CPC classification number: H01L29/7848 ,  H01L21/3086 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78

    Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

    Abstract translation: 提供一种形成半导体器件的方法。 在基板上设置至少一个层叠结构。 第一间隔物层，第二间隔物层和第三间隔物层依次形成在基板上并覆盖层叠结构。 第一，第二和第三间隔物材料层被蚀刻以在堆叠结构的侧壁上形成三层间隔结构。 三层间隔结构包括从层叠结构的一侧形成第一间隔物，第二间隔物和第三间隔物，第二间隔物的介电常数小于第一间隔物的介电常数和 第三间隔物的介电常数。

    Method of fabricating semiconductor device structure
    5.
    发明授权
    Method of fabricating semiconductor device structure 有权
    制造半导体器件结构的方法

    公开(公告)号：US09018066B2

    公开(公告)日：2015-04-28

    申请号：US14042224

    申请日：2013-09-30

    Applicant: United Microelectronics Corp.

    Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Shih-Fang Tzou

    IPC: H01L21/336 ,  H01L21/28 ,  H01L29/66 ,  H01L21/311

    CPC classification number: H01L21/31111 ,  H01L21/3086 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

    Abstract translation: 提供一种制造半导体器件结构的方法。 该方法包括以下步骤。 在基板上形成栅极电介质层。 栅极电极位于栅极电介质层上。 处理由栅电极露出的栅介电层。 执行第一蚀刻工艺以去除由栅电极暴露的栅介质层的至少一部分。 在栅电极的侧壁上形成间隔物。 执行第二蚀刻工艺以在栅电极旁边的基板中形成凹部。 此外，在第一蚀刻工艺和第二蚀刻工艺期间，经处理的栅极电介质层的蚀刻速率大于未处理的栅极介电层的蚀刻速率。

    Method of forming fin-shaped structure
    6.
    发明授权
    Method of forming fin-shaped structure 有权

    公开(公告)号：US10930517B2

    公开(公告)日：2021-02-23

    申请号：US16532477

    申请日：2019-08-06

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Wen-Jiun Shen ,  Ssu-I Fu ,  Yen-Liang Wu ,  Chia-Jong Liu ,  Yu-Hsiang Hung ,  Chung-Fu Chang ,  Man-Ling Lu ,  Yi-Wei Chen

    IPC: H01L21/77 ,  H01L21/308 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.

    Semiconductor device having metal gate
    9.
    发明授权
    Semiconductor device having metal gate 有权

    公开(公告)号：US10186594B2

    公开(公告)日：2019-01-22

    申请号：US15641312

    申请日：2017-07-04

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chun-Ting Chiang ,  Chi-Ju Lee ,  Chih-Wei Lin ,  Bo-Yu Su ,  Yen-Liang Wu ,  Wen-Tsung Chang ,  Jui-Ming Yang ,  I-Fan Chang

    IPC: H01L21/28 ,  H01L29/49 ,  H01L21/02

    Abstract: The present invention provides a method of manufacturing a gate stack structure. The method comprises providing a substrate. A dielectric layer is then formed on the substrate and a gate trench is formed in the dielectric layer. A bottom barrier layer, a first work function metal layer and a top barrier layer are formed in the gate trench in sequence. Afterwards, a silicon formation layer is formed on the top barrier layer and filling the gate trench. A planarization process is performed, to remove a portion of the silicon formation layer, a portion of the bottom barrier layer, a portion of the first work function metal layer, and a portion of the top barrier layer. Next, the remaining silicon formation layer is removed completely, and a conductive layer is filled in the gate trench.

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