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    HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE
    21.
    发明申请
    HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE 有权
    高电压金属氧化物半导体晶体管器件

    公开(公告)号：US20140091389A1

    公开(公告)日：2014-04-03

    申请号：US13629608

    申请日：2012-09-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ming-Shun Hsu ,  Ke-Feng Lin ,  Chiu-Te Lee ,  Chih-Chung Wang

    IPC: H01L29/78

    CPC classification number: H01L29/0878 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/7816

    Abstract: A high voltage metal-oxide-semiconductor transistor device includes a substrate having an insulating region formed therein, a gate covering a portion of the insulating region and formed on the substrate, a source region and a drain region formed at respective sides of the gate in the substrate, a body region formed in the substrate and partially overlapped by the gate, and a first implant region formed in the substrate underneath the gate and adjacent to the body region. The substrate and body region include a first conductivity type. The source region, the drain region, and the first implant region include a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

    Abstract translation: 高电压金属氧化物半导体晶体管器件包括其中形成有绝缘区域的衬底，覆盖绝缘区域的一部分并形成在衬底上的栅极，形成在栅极各侧的源极区域和漏极区域 基板，形成在基板中并与栅极部分重叠的主体区域，以及形成在栅极下方并与主体区域相邻的基板中的第一注入区域。 衬底和体区包括第一导电类型。 源极区域，漏极区域和第一注入区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。

    Exposure method of semiconductor pattern
    22.
    发明申请
    Exposure method of semiconductor pattern 有权

    公开(公告)号：US20250102922A1

    公开(公告)日：2025-03-27

    申请号：US18382528

    申请日：2023-10-22

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shin-Hung Li ,  Ruei-Jhe Tsao ,  Shan-Shi Huang ,  Wen-Fang Lee ,  Chiu-Te Lee

    IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033

    Abstract: The invention provides an exposure method of semiconductor patterns, which comprises the following steps: providing a substrate, performing a first exposure step with a first photomask, forming a first pattern in a first region on the substrate, and performing a second exposure step with a second photomask, forming a second pattern in a second region on the substrate, the first pattern and the second pattern are in contact with each other, and at an interface of the first region And the second region, the first pattern and the second pattern are aligned with each other.

    High voltage semiconductor devices with Schottky diodes
    28.
    发明授权
    High voltage semiconductor devices with Schottky diodes 有权
    具有肖特基二极管的高压半导体器件

    公开(公告)号：US09196723B1

    公开(公告)日：2015-11-24

    申请号：US14564050

    申请日：2014-12-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Kuan-Yu Chen ,  Tseng-Hsun Liu ,  Min-Hsuan Tsai ,  Te-Chang Chiu ,  Chiu-Ling Lee ,  Chiu-Te Lee

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/45

    CPC classification number: H01L29/782 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1079 ,  H01L29/45 ,  H01L29/665 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7823 ,  H01L29/872

    Abstract: The present invention provides a semiconductor device structure which integrates a lateral diffused metal oxide semiconductor (LDMOS) with a Schottky diode, including: a substrate, having a first conductivity type, a gate positioned on the substrate, a drain region formed in the substrate, the drain region having a second conductivity type complementary to the first conductivity type, a source region formed in the substrate, the source region having the second conductivity type, a high-voltage well region formed in the substrate, the high-voltage well region having a first conductivity type; a Schottky diode disposed on the substrate and disposed beside the LDMOS, wherein the semiconductor device structure is an asymmetric structure, and a deep well region disposed in the substrate and having the second conductivity type, wherein the LDMOS and the Schottky diode are all formed within the deep well region.

    Abstract translation: 本发明提供了一种将横向扩散金属氧化物半导体（LDMOS）与肖特基二极管集成的半导体器件结构，包括：具有第一导电类型的衬底，位于衬底上的栅极，形成在衬底中的漏极区， 所述漏极区域具有与所述第一导电类型互补的第二导电类型，形成在所述衬底中的源极区域，具有第二导电类型的源极区域，形成在所述衬底中的高压阱区域，所述高压阱区域具有 第一导电类型; 设置在衬底上并设置在LDMOS旁边的肖特基二极管，其中半导体器件结构是不对称结构，以及设置在衬底中并且具有第二导电类型的深阱区，其中LDMOS和肖特基二极管全部形成在 深井区域。

    Semiconductor structure
    29.
    发明授权
    Semiconductor structure 有权
    半导体结构

    公开(公告)号：US09136375B2

    公开(公告)日：2015-09-15

    申请号：US14085939

    申请日：2013-11-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

    CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

    Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

    SEMICONDUCTOR STRUCTURE
    30.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权
    半导体结构

    公开(公告)号：US20150137228A1

    公开(公告)日：2015-05-21

    申请号：US14085939

    申请日：2013-11-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chiu-Te Lee ,  Ming-Shun Hsu ,  Ke-Feng Lin ,  Chih-Chung Wang ,  Hsuan-Po Liao ,  Shih-Teng Huang ,  Shu-Wen Lin ,  Su-Hwa Tsai ,  Shih-Yin Hsiao

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

    CPC classification number: H01L29/7816 ,  H01L21/823425 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095

    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

    Abstract translation: 提供半导体结构。 半导体结构包括衬底，在衬底中形成的深阱，在深阱中形成的第一阱和第二阱，形成在衬底上并设置在第一阱和第二阱之间的栅电极，第一隔离， 和第二个隔离。 第二口井与第一口井隔开。 第一隔离件从衬底的表面向下延伸并且设置在栅电极和第二阱之间。 第二隔离件从衬底的表面向下延伸并与第一阱相邻。 第一隔离深度与第二隔离深度之比小于1。

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