公开(公告)号：GB2486701A

公开(公告)日：2012-06-27

申请号：GB201021810

申请日：2010-12-23

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

IPC: H02M1/00 ,  H02M3/07

Abstract: A bipolar output charge pump circuit 100 is provided having a network of switching paths 110 for selectively connecting an input node VV and a reference node VG for connection to an input voltage, a first pair of output nodes VP, VN and a second pair of output nodes VQ, VM, and two pairs of flying capacitor nodes CF1A, CF1B; CF2A, CF2B, and a controller 120 for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors CF1 , CF2 connected to the two pairs of flying capacitor nodes, to provide a first bipolar output voltage at the first pair of output nodes and a second bipolar output voltage at the second pair of bipolar output nodes.

公开(公告)号：GB2478458B

公开(公告)日：2011-12-07

申请号：GB201108798

申请日：2006-12-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H02M3/07

Abstract: A charge pump circuit, and associated method and apparatuses, for providing a split-rail voltage supply, the circuit having a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of said states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

公开(公告)号：GB2478458A8

公开(公告)日：2011-09-28

申请号：GB201108798

申请日：2006-12-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H02M3/07

Abstract: A charge pump circuit, and associated method and apparatuses, for providing a split-rail voltage supply, the circuit having a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of said states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage and centered on the voltage at the common terminal.

公开(公告)号：GB2446843B

公开(公告)日：2011-09-07

申请号：GB0625955

申请日：2006-12-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

IPC: H03F1/02 ,  H02M3/07 ,  H03G1/00

Abstract: A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage.

公开(公告)号：HK1147855A1

公开(公告)日：2011-08-19

申请号：HK11101742

申请日：2011-02-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

IPC: H02M20060101

公开(公告)号：GB2472701B

公开(公告)日：2011-07-20

申请号：GB201014826

申请日：2006-12-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

IPC: H02M3/07

公开(公告)号：GB2475633A

公开(公告)日：2011-05-25

申请号：GB201102622

申请日：2006-12-22

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL ,  PENNOCK JOHN LAURENCE ,  FRITH PETER JOHN

IPC: H03F1/02 ,  H02M3/07 ,  H03F3/187 ,  H03F3/213

Abstract: An audio amplifier may be used to drive either low impedance loads such as headphones with 32 Ohm impedance (figure 1a) or high impedance loads such as the 10 kOhm input impedance of an external amplifier (figures 1b or 1c). The dual mode charge pump 10 provides lower supply voltages to the amplifier when the loads are of low impedance. The charge pump may provide supplies of plus and minus VDD or plus and minus VDD/2 from a single VDD input. The dual mode charge pump may use only one flying capacitor in both modes (figures 4-13) or may use two flying capacitors in both modes (figures 14-23).

公开(公告)号：GB2466283A

公开(公告)日：2010-06-23

申请号：GB0823146

申请日：2008-12-18

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03L7/093 ,  H03H11/48

Abstract: A phase locked loop (PLL) has an input 12, a phase detector 14, a charge pump 16, a loop filter 18 and a voltage controlled oscillator (VCO) 20 connected to the output 22 of the loop. The voltage controlled oscillator 20 is connected to variable divider 24 in the feedback path of the loop. The PLL is characterized in that a property of the loop filter 18, such as an effective capacitance value 30, is controlled based on a value of the controllable frequency division ratio. The capacitance value 30 may be scaled by a current mirror circuit (fig.3). The current mirror circuit may be controlled by a control signal derived from the frequency division ratio via a look up table 38. The invention achieves a reduction in the area required for the capacitor of the loop filter.

公开(公告)号：GB2434930B

公开(公告)日：2009-08-26

申请号：GB0601973

申请日：2006-02-01

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03L7/081

Abstract: A delay-locked loop (DLL) circuit has a reference signal input for a receiving a periodic reference signal and a number of signal outputs for outputting respective output signals derived from the reference signal and having a desired phase relationship with one another. The DLL circuit comprises a voltage controlled delay line (VCDL) comprising a plurality of identical delay stages connected in series, and a feedback loop including a phase comparator for controlling the VCDL such that the total delay over a number of stages matches the period of the periodic reference signal. Signal outputs are connected to derive their respective output signals from respective nodes within said delay line. The phase comparator compares the phase of first and second differently delayed versions of the reference signal from respective nodes within the variable delay line separated only by a plurality of identical delay stages. Duty cycle distortion is minimised as a result. Start-up control circuitry is arranged (i) to minimise the delay of the variable delay line prior to starting operation and (ii) to cause said phase comparator to ignore a first transition in one signal, in determining the relative order of transitions in the compared signals. False locking and harmonic locking are thus eliminated while permitting a very wide range of input frequencies.

公开(公告)号：GB2451536B

公开(公告)日：2009-07-15

申请号：GB0806471

申请日：2008-04-09

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： LESSO JOHN PAUL

IPC: H03F1/02 ,  H02M3/07 ,  H03F1/26 ,  H03F1/30

Abstract: An amplifier circuit comprises an input, for receiving an input signal to be amplified; a preamplifier, for amplifying the input signal based on a variable gain; a power amplifier for amplifying the signal output from the preamplifier; and a variable voltage power supply for supplying one or more supply voltages to the power amplifier. The supply voltages are adjusted based on the variable gain or the input digital signal. According to other aspects of the invention, a power supply of an amplifier circuit is clocked using a clock signal, whereby the clock signal has a frequency that varies in accordance with a volume signal or an input signal.