公开(公告)号：KR1020060131395A

公开(公告)日：2006-12-20

申请号：KR1020050051818

申请日：2005-06-16

Applicant: 한국과학기술원

Inventor： 조규형 ,  김이경 ,  곽태우 ,  이광찬 ,  김성은

IPC: H03M1/70

CPC classification number: H03M1/1023 ,  H03M1/662 ,  H03M1/70 ,  H03M2201/63 ,  H03M2201/8152

Abstract: An MDAC circuit capable of correcting a gain error of residual voltage and a sample/hold circuit are provided to correct the gain error of the residual voltage due to insufficient gain of an operation amplifier by using a variable capacitor. An MDAC(Multiplying Digital/Analog Converter) circuit includes a sampling capacitor(Cs), a feedback capacitor(Cf), and an operation amplifier(OPA). A gain compensation unit is connected in parallel with the sampling capacitor. The gain compensation unit samples an analog input signal at a sampling phase, and is connected to plural reference voltages at an amplifying phase, thereby compensating a gain of the operation amplifier. A switching member is switched according to a switch control signal input from an exterior.

Abstract translation: 提供能够校正残余电压的增益误差的MDAC电路和采样/保持电路，以通过使用可变电容器来校正由于运算放大器的增益不足引起的残余电压的增益误差。 MDAC（乘法数字/模拟转换器）电路包括采样电容器（Cs），反馈电容器（Cf）和运算放大器（OPA）。 增益补偿单元与采样电容并联。 增益补偿单元以采样相位采样模拟输入信号，并以放大相连接到多个参考电压，从而补偿运算放大器的增益。 根据从外部输入的开关控制信号来切换开关构件。

公开(公告)号：KR1020010008374A

公开(公告)日：2001-02-05

申请号：KR1020000071360

申请日：2000-11-28

Applicant: 주식회사 나노위즈

Inventor： 전영득 ,  유상민 ,  이승훈 ,  주상백

IPC: H03M1/12

CPC classification number: H03M1/14 ,  H03M2201/8152 ,  H03M2201/932

Abstract: PURPOSE: A merged capacitor switching structure of a pipeline analog to digital converter is provided to reduce a load capacitance by merging two capacitors to reduce the number of the required capacitors, thereby increasing the speed of an amplifier by two times without increasing the power consumption. CONSTITUTION: The device is composed of a plurality of capacitors(C1-C16) for storing an analog input voltage, an amplifier for amplifying and outputting a residual voltage through the capacitors, a 4 bits of flash converter(50) connected to an input terminal and a decoding circuit(60) for controlling a switch depending on a digital code. The merged capacitor switching structure merges two capacitors(C1,C2) in which an identical voltage is applied and the stored charge amount is same among the plurality of capacitors, and forms one capacitor(C1'), wherein a capacitor(C2') is grounded.

Abstract translation: 目的：提供一种流水线模数转换器的并联电容器开关结构，通过合并两个电容来减少负载电容，减少所需电容的数量，从而将放大器的速度提高两倍，而不增加功耗。 构成：该装置由用于存储模拟输入电压的多个电容器（C1-C16），用于放大并通过电容器输出剩余电压的放大器组成，连接到输入端子的4位闪存转换器（50） 以及用于根据数字代码控制开关的解码电路（60）。 合并电容器开关结构合并在多个电容器中施加相同电压的两个电容器（C1，C2）和存储的电荷量相同，形成一个电容器（C1'），其中电容器（C2'）为 接地。