公开(公告)号：WO1996037821A1

公开(公告)日：1996-11-28

申请号：PCT/US1996007589

申请日：1996-05-23

Applicant: NATIONAL SEMICONDUCTOR CORPORATION

Inventor： NATIONAL SEMICONDUCTOR CORPORATION ,  PHILLIPS, Christopher, E.

IPC: G06F05/06

CPC classification number: G06F7/764 ,  G06F5/12 ,  G06F2205/126

Abstract: An availability status indicator circuit simultaneously indicates which of N circular buffer cells (CBCx, for x = 0 through N-1) are available for access. N cell status circuits are provided that correspond to the separate circular buffer cells. Each cell status circuit includes an output terminal at which a cell availability status signal is provided to indicate the availability status of the corresponding circular buffer cell. A first input terminal of the cell status circuit is connected to receive the cell availability status signal from the previous cell status circuit. The cell availability status signal is generated in response to the cell availability status signal of the previous cell, to an available address indicator signal that includes an indicator of whether the corresponding circular buffer cell is a first circular buffer cell available to be accessed, and to an unavailable address indicator signal that includes an indicator of whether the corresponding circular buffer cell is a last circular buffer cell available to be accessed. The cell availability status signal has a first state if the corresponding circular buffer cell is available for access and has a second state if the corresponding circular buffer cell is not available for access.

Abstract translation: 可用性状态指示电路同时指示N个循环缓冲单元（CBCx，x = 0到N-1）中的哪一个可用于访问。 提供对应于单独的循环缓冲单元的N个单元状态电路。 每个单元状态电路包括输出端子，在该输出端子处提供单元可用性状态信号以指示相应循环缓冲单元的可用性状态。 连接单元状态电路的第一输入端，从前一单元状态电路接收单元可用状态信号。 响应于先前小区的小区可用性状态信号而产生小区可用性状态信号到可用的地址指示符信号，该可用地址指示符信号包括对应的循环缓冲区是否是可访问的第一循环缓冲区，以及 一个不可用的地址指示符信号，其包括对应的循环缓冲区是否是可访问的最后一个循环缓冲区的指示符。 如果对应的循环缓冲区可用于访问，则小区可用性状态信号具有第一状态，并且如果相应的循环缓冲区不可用于访问，则具有第二状态。

公开(公告)号：WO1996025703A1

公开(公告)日：1996-08-22

申请号：PCT/DE1996000179

申请日：1996-02-06

Applicant: SIEMENS NIXDORF INFORMATIONSSYSTEME AG ,  HEINRICHS, Hans-Jürgen

Inventor： SIEMENS NIXDORF INFORMATIONSSYSTEME AG

IPC: G06F05/06

CPC classification number: G06F5/12 ,  G06F2205/126

Abstract: The invention concerns a method and a device for buffering between two synchronously clocked devices which send and receive data word packets, output being enabled as soon as the number of output clock pulses after the beginning of a data packet exceeds a starting value which is previously determined by measuring the output clock pulses as a function of the input clock pulses.

Abstract translation: 两个之间的缓冲的方法和装置时钟同步，数据字传输和接收装置，数据分组，其中，当一个数据分组的开始后输出的时钟周期的数量超过，预先通过测量输出时钟作为输入时钟某些开始值的函数的输出被使能。

公开(公告)号：WO1996023252A1

公开(公告)日：1996-08-01

申请号：PCT/SE1996000049

申请日：1996-01-19

Applicant: TELEFONAKTIEBOLAGET LM ERICSSON ,  ARVIDSSON, Carl-Erik ,  LINDBLOM, Martin

Inventor： TELEFONAKTIEBOLAGET LM ERICSSON

IPC: G06F05/06

CPC classification number: G06F5/10 ,  G06F2205/106 ,  G11C8/00

Abstract: A data buffer includes a number of data storing elements (202), a tree shaped structure (218) of multiplexer elements (216), a write address generator (21), and a read address generator (214). The data storing elements have data inputs connected in parallel to an input for a data stream from a sending clock domain. The tree shaped structure of multiplexer elements is arranged for receiving data from the data storing elements, and emits on an output a data stream to a receiving clock domain. The write address generator generates, controlled by a write clock signal (C1) from the clock of the sending clock domain, write addresses for entering data from the sending clock domain into the data storing elements, one at a time. The read address generator generates, controlled by a read clock signal (c2) from the clock generator of the receiving clock domain, read addresses for reading out data from the data storing elements in the same order as they were read in.

Abstract translation: 数据缓冲器包括多个数据存储元件（202），多路复用器元件（218）的树形结构（218），写地址生成器（21）和读地址生成器（214）。 数据存储元件具有与来自发送时钟域的数据流的输入并行连接的数据输入。 多路复用器元件的树形结构被布置用于从数据存储元件接收数据，并将数据流输出到接收时钟域。 写地址生成器由来自发送时钟域的时钟的写入时钟信号（C1）产生，用于将数据从发送时钟域输入数据存储元件的写入地址，一次一个。 读取地址生成器由接收时钟域的时钟发生器的读取时钟信号（c2）产生，读取地址用于从与数据存储元件读取的数据相同的顺序读出数据。

公开(公告)号：WO1992015055A1

公开(公告)日：1992-09-03

申请号：PCT/DE1992000071

申请日：1992-02-05

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  PFEIFFER, Klaus ,  KOSLER, Wolfgang

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F05/06

CPC classification number: G06F5/12 ,  G06F2205/126

Abstract: Disclosed is a circuit designed to connect a microprocessor system (MP) to a communications channel (K) for series data transmission, the circuit ensuring optimum data transmission. This is done by the use of two first-in/first-out memories (F1, F2) with adjustable threshold capacity levels.

公开(公告)号：WO1992008186A1

公开(公告)日：1992-05-14

申请号：PCT/US1991008102

申请日：1991-11-01

Applicant: ANALOG DEVICES, INC.

Inventor： ANALOG DEVICES, INC. ,  GARDE, Douglas

IPC: G06F05/06

CPC classification number: G06F5/10 ,  G06F7/72 ,  G06F9/3552 ,  G06F2205/106

Abstract: The invention comprises a hardware constructed address generator for a circular buffer which can be of any size and be in any position in memory. The address generator calculates both an absolute value and a wrapped value and selects one in accordance with whether the wrapped value falls within the boundaries of the buffer.

Abstract translation: 本发明包括用于圆形缓冲器的硬件构造的地址发生器，其可以是任何大小并且在存储器中的任何位置。 地址生成器计算绝对值和包装值，并根据包装值是否落在缓冲区的边界内选择一个。

公开(公告)号：WO1991013397A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001251

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  EIDLER, Chris, W. ,  JOHNSON, Hoke, S., III ,  SHAH, Kaushik, S.

IPC: G06F05/06

CPC classification number: G06F5/10 ,  G06F3/0601 ,  G06F5/00 ,  G06F2003/0691

Abstract: A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.

Abstract translation: 一种用于经由分段存储器和直接存储器存取（DMA）通道的元件将数据从一个设备接口传送到另一个设备接口的方法和装置。