公开(公告)号：WO1991017506A1

公开(公告)日：1991-11-14

申请号：PCT/US1991002314

申请日：1991-04-03

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  POWERS, David, T. ,  JAFFE, David, H. ,  HENSON, Larry, P. ,  JOHNSON, Hoke, S., III ,  GLIDER, Joseph, S. ,  IDLEMAN, Thomas, E.

IPC: G06F13/12

CPC classification number: G06F11/2092 ,  G06F11/0757 ,  G06F11/1076 ,  G06F11/2033 ,  G11B20/1833

Abstract: A method and apparatus for controlling data flow between a computer (10) and a group of memory devices (18A...18M) arranged in a particular logical configuration. The system includes a group of first level controllers (12A, 12B) and a group of second level controllers (14A, 14B). The first level controllers (12A, 12B) and the second level controllers (14A, 14B) work together such that if one of the second level controllers (14a, 14B) fails, the routing between the first level controllers (12A, 12B) and the memory devices (18A...18M) is switched to a properly functioning second level controller (14A, 14B) without the need to involve the computer (10) in the rerouting process. The logical configuration of the memory devices (18A...18M) remains constant. The invention also includes switching circuitry (16A1...16M6) which permits a functioning second level controller (14A, 14B) to assume control of a group of memory devices (18A...18M) formerly controlled by the failed second level controller (14A, 14B).

公开(公告)号：WO1991015825A1

公开(公告)日：1991-10-17

申请号：PCT/US1991001255

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  GAJJAR, Kumar ,  SHAH, Kaushik, S. ,  TRANG, Duc, H.

IPC: G06F13/42

CPC classification number: G06F3/0601 ,  G06F13/4213 ,  G06F13/4226 ,  G06F2003/0692

Abstract: An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Abstract translation: 提供了部分基于SCSI标准的改进的接口系统。 单个电缆数据总线同时在两个设备之间传输几个字节的信息。 接口系统在单个并行传输中传输多字节命令，消息，状态信息或数据。 提供微定序器以允许跨接口的数据传输，而不需要来自转移涉及的设备中的处理器的繁重的注意。

公开(公告)号：WO1991001597A1

公开(公告)日：1991-02-07

申请号：PCT/US1990003629

申请日：1990-06-26

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  JOHNSON, Hoke, Stephens, III

IPC: H03M05/12

CPC classification number: H03M5/12

Abstract: A circuit for decoding a high speed Manchester encoded digital communication signal is provided. The circuit includes a pair of latch circuits which are used to detect clock edges in the encoded signal for providing respectively set and reset pulses to a third latch circuit, an output of which comprises the decoded data of the Manchester code signal. Additional logic is provided to extract a clock signal from the Manchester code signal.

公开(公告)号：WO1991015069A1

公开(公告)日：1991-10-03

申请号：PCT/US1991001310

申请日：1991-02-28

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  JAFFE, David, H. ,  JOHNSON, Hoke, S., III ,  EIDLER, Chris, W.

IPC: H04L12/40

CPC classification number: H04L12/4015 ,  H04L12/407 ,  H04L12/413 ,  H04L47/10 ,  H04L47/11 ,  H04L47/13 ,  H04L47/29

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node (10) sharing a CSMA communication medium (14) is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit (100) from seeking access if total transmission activity (TCU) on the communication medium exceeds a total use threshold (TMU) value and transmission activity (LCS) of the node exceeds a local use threshold value (LMS), and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Abstract translation: 提供了一种调度机制，用于在节点（10）共享CSMA通信介质（14）的仲裁电路何时开始CSMA仲裁以便一旦该节点具有准备传输的消息，则调度机制将启动CSMA仲裁以访问通信介质，调度机制延迟 如果通信介质上的总传输活动（TCU）超过节点的总使用阈值（TMU）值和传输活动（LCS）超过本地使用阈值（LMS），则仲裁电路（100）寻求访问，否则 允许仲裁电路根据分配给节点的优先级值通过仲裁寻求对通信介质的访问。

公开(公告)号：WO1991014229A1

公开(公告)日：1991-09-19

申请号：PCT/US1991001256

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  GLIDER, Joseph, S. ,  IDLEMAN, Thomas, E.

IPC: G06F13/12

CPC classification number: G06F11/2005 ,  G06F11/2007 ,  G06F11/2089 ,  G06F13/4022

Abstract: A network-type (10) data processing system is provided. The system can support multiple simultaneous exchanges of data, and includes multi-port storage devices (100-104) in which all ports can be active at all times. On initialization of the system, each storage device can announce itself through all of its ports simultaneously through at least 2 paths.

Abstract translation: 提供了一种网络型（​​10）数据处理系统。 该系统可以支持多个数据同时交换，并且包括所有端口始终处于活动状态的多端口存储设备（100-104）。 在系统初始化时，每个存储设备可以通过至少2个路径同时通过其所有端口通知其自身。

公开(公告)号：WO1991013397A1

公开(公告)日：1991-09-05

申请号：PCT/US1991001251

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  EIDLER, Chris, W. ,  JOHNSON, Hoke, S., III ,  SHAH, Kaushik, S.

IPC: G06F05/06

CPC classification number: G06F5/10 ,  G06F3/0601 ,  G06F5/00 ,  G06F2003/0691

Abstract: A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.

Abstract translation: 一种用于经由分段存储器和直接存储器存取（DMA）通道的元件将数据从一个设备接口传送到另一个设备接口的方法和装置。

公开(公告)号：WO1991015824A1

公开(公告)日：1991-10-17

申请号：PCT/US1991002316

申请日：1991-04-03

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  HENSON, Larry, P. ,  GAJJAR, Kumar ,  IDLEMAN, Thomas, E.

IPC: G06F13/18

CPC classification number: G06F13/374 ,  G06F13/36

Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus (16), where the bus (16) has control and arbitration functions distributed among the devices (20) coupled to the bus (16), with each device (20) having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus (16) by a plurality of SCSI devices (20) coupled to the bus (16) by providing a pseudo busy signal to SCSI devices (20) from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices (20) and control the order in which the devices (20) will be serviced when ready.

Abstract translation: 本发明提供了一种用于动态地修改对总线（16）的访问的优先级的方法和装置，其中总线（16）具有分配在耦合到总线（16）的设备（20）中的控制和仲裁功能，每个 装置（20）具有固定的优先级。 选择性地禁止由特定设备访问总线，防止它们断言其固定的优先级。 在优选实施例中，本发明通过向SCSI设备（20）提供伪忙信号来提供通过耦合到总线（16）的多个SCSI设备（20）来重新选择SCSI总线（16）的控制，SCSI设备 不需要重新选择。 以这种方式，启动器可以向SCSI设备（20）发出多个命令，并且在准备好时控制设备（20）将被服务的顺序。

公开(公告)号：WO1991015823A1

公开(公告)日：1991-10-17

申请号：PCT/US1991002317

申请日：1991-04-03

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  GLIDER, Joseph, S. ,  JAFFE, David, H.

IPC: G06F11/22

CPC classification number: G06F9/5011 ,  G06F11/22 ,  G06F2209/503

Abstract: A computing system providing resource management in a multiple resource system. In the preferred embodiment, the computing system has a plurality of resources (106, 108, 138a, 140a, 142a, 126a-126m) for storing, transmitting or manipulating data. The system also has a fault management subsystem (122a, 150, 152) that accesses and operates the resources when the resources are in a first availability state and an operational subsystem for accessing and operating the resources when the resources are in a second availability state. The system has a mechanism (200, 118, 152) for providing real time sharing of any of the resources between the fault management subsystem (122a, 150, 152) and the operational subsystem without disrupting the services provided by the operational subsystem. In addition, the system has a mechanism for representing the operational interdependencies of the resources by organizing the resources in a logical structure in which each resource is a node conceptually connected to at least one other resource.

公开(公告)号：WO1991015822A1

公开(公告)日：1991-10-17

申请号：PCT/US1991002315

申请日：1991-04-03

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  HENSON, Larry, P. ,  GAJJAR, Kumar ,  POWERS, David, T. ,  IDLEMAN, Thomas, E.

IPC: G06F11/20

CPC classification number: G06F11/10 ,  G06F11/0757 ,  G06F11/1076 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/201 ,  G06F11/2089 ,  G06F11/2094 ,  G06F2211/1057 ,  G11B20/1833

Abstract: A mass memory system for digital computers is disclosed. The system has a plurality of disk drives (250-255) coupled to a plurality of small buffers (240-245). An Error Correction Controller (260 and 270) is coupled to a plurality of X-bar switches (210-215), the X-bar switches being connected between each disk drive and its buffers. Data is read from and written to the disk drives in parallel and error correction is also performed in parallel. The X-bar switches are used to couple and decouple functional and nonfunctional disk drives to the system as necessary. Likewise, the buffers can be disconnected from the system should they fail. The parallel architecture, combined with a Reed-Solomon error detection and correction scheme and X-bar switches allows the system to tolerate and correct any two failed drives, allowing for high fault-tolerance operation.

公开(公告)号：WO1991014982A1

公开(公告)日：1991-10-03

申请号：PCT/US1991001253

申请日：1991-02-27

Applicant: SF2 CORPORATION

Inventor： SF2 CORPORATION ,  JAFFE, David, H. ,  POWERS, David, T. ,  GLIDER, Joseph, S. ,  IDLEMAN, Thomas, E.

IPC: G06F03/06

CPC classification number: G06F3/0601 ,  G06F11/006 ,  G06F2003/0692 ,  G11B20/1833

Abstract: A method and apparatus for identifying members of a set of physical mass storage devices acting as one logical mass storage device are provided. Each physical mass storage device is assigned a membership signature identifying it as a valid member of the set. Whenever a member of a set undergoes a membership state-changing event, the membership signatures of all other devices in the set are changed, so that the member with the changed membership state no longer has a valid signature. When the member is reinstalled, it can be given a new valid signature after it is uptdated or regenerated.

Abstract translation: 提供了一种用于识别充当一个逻辑大容量存储设备的一组物理大容量存储设备的成员的方法和装置。 为每个物理大容量存储设备分配一个会员签名，将其标识为集合的有效成员。 每当一个成员的成员经历会员状态改变事件时，组中所有其他设备的成员签名被改变，使得具有改变的成员资格状态的成员不再具有有效的签名。 重新安装成员后，可以在升级或重新生成新的有效签名后再给予新的有效签名。